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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. the information in this document is subject to change without notice. mos integrated circuit document no. u13233ej1v1ds00 (1st edition) (previous no. ic-3580) date published january 1998 n cp(k) printed in japan small, general-purpose 4-bit single-chip microcontrollers m pd17145(a1), 17147(a1), 17149(a1) the m pd17145(a1), 17147(a1), and 17149(a1) are 4-bit single-chip microcontrollers integrating an 8-bit a/d converter (4 channels), a timer function (3 channels), and a serial interface. these microcontrollers employ a cpu of the general-purpose register type that can execute direct memory operations and direct memory-to-memory data transfer for efficient programming. all the instructions consist of 16 bits per word. in addition, a one-time prom version, the m pd17p149, is also available for program evaluation. the functions of these microcontrollers are described in detail in the following users manual. be sure to read the following manual when designing your system: m pd17145 subseries users manual: ieu-1383 features ? 17k architecture : general-purpose register type : instruction length fixed to 16 bits ? program memory (rom) : m pd17145(a1) : 2 kb (1024 16 bits) : m pd17147(a1) : 4 kb (2048 16 bits) : m pd17149(a1) : 8 kb (4096 16 bits) ? data memory (ram) : 110 4 bits ? external interrupt : 1 (int pin, with sense input) ? instruction execution time : 2 m s (at 8 mhz: ceramic oscillation) ? 8-bit a/d converter : 4 channels, absolute accuracy: 1.5 lsb max. (v dd = 4.0 to 5.5 v) ? timer : 3 channels ? serial interface : 1 channel (clocked 3-wire) ? poc circuit (mask option) ? operating voltage : v dd = 2.7 to 5.5 v (at 400 khz to 2 mhz) :v dd = 4.5 to 5.5 v (at 400 khz to 8 mhz) ? operating temperature : t a = C40 to +110 ?c applications automotive electronics, etc. unless contextually excluded, references in this data sheet to the m pd17149 (a1) mean the m pd17145 (a1) and m pd17147 (a1). 1995 data sheet 2 m pd17145(a1), 17147(a1), 17149(a1) ordering information remark indicates rom code suffix. part number package quality grade m pd17145ct(a1)- 28-pin plastic shrink dip (400 mil) special m pd17145gt(a1)- 28-pin plastic sop (375 mil) special m pd17147ct(a1)- 28-pin plastic shrink dip (400 mil) special m pd17147gt(a1)- 28-pin plastic sop (375 mil) special m pd17149ct(a1)- 28-pin plastic shrink dip (400 mil) special m pd17149gt(a1)- 28-pin plastic sop (375 mil) special please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. 3 m pd17145(a1), 17147(a1), 17149(a1) poc circuit operating voltage package one-time prom version m pd17p149 timer 3 channels internal interrupt: 4 function list part number m pd17145 (a1) m pd17147 (a1) m pd17149 (a1) item rom capacity 2 kb (1024 16 bits) 4 kb (2048 16 bits) 8 kb (4096 16 bits) ram capacity 110 4 bits stack address stack 5, interrupt stack 3 i/o : 20 i/o ports 23 input : 2 sense input (int pin note ):1 a/d converter input 4 channels (shared with port pins), absolute accuracy: 1.5 lsb max. ? 8-bit timer/counter: 2 channels (can be used as 1 channel of 16-bit timer) ? 7-bit basic interval timer: 1 channel (can be used as watchdog timer) serial interface 1 channel (3-wire) ? multiple interrupt by hardware (3 levels max.) ? external interrupt (int): 1 rising edge, falling edge, or both rising and falling edges selectable for detection. interrupt ? timer 0 (tm0) ? timer 1 (tm1) ? basic interval timer (btm) ? serial interface (sio) instruction execution time 2 m s (at 8 mhz, ceramic oscillation) standby function halt, stop mask option (can be used in application circuit that operates on v dd = 5 v 10 %, 400 khz to 4 mhz) 2.7 to 5.5 v (at 400 khz to 2 mhz) 4.5 to 5.5 v (at 400 khz to 8 mhz) 28-pin plastic shrink dip (400 mil) 28-pin plastic sop (375 mil) quality grade is "standard" and not (a1). operating temperature range: t a = C40 to +85 ?c note the int pin is used as an input pin (sense input) when the external interrupt function is not used. the status of this pin is read by using the int flag of a control register, not by a port register. caution the prom version is functionally compatible with the mask rom versions but its internal circuit and part of the electrical characteristics are different from those of the mask rom versions. to replace the prom version with a mask rom version, thoroughly conduct application evaluation by using a sample of the mask rom version. 4 m pd17145(a1), 17147(a1), 17149(a1) pin configuration (top view) 28-pin plastic shrink dip (400 mil) 28-pin plastic sop (375 mil) adc 0 -adc 3 : analog input gnd : ground int : external interrupt input p0a 0 to p0a 3 : port 0a p0b 0 to p0b 3 : port 0b p0c 0 to p0c 3 : port 0c p0d 0 to p0d 3 : port 0d p0e 0 to p0e 3 : port 0e p0f 0 and p0f 1 : port 0f reset : reset input rls : standby release signal input sck : serial clock i/o si : serial data input so : serial data output tm1out : timer 1 output v dd : power v ref : a/d converter reference voltage x in , x out : for system clock oscillation v dd p0f 1 /v ref p0c 3 /adc 3 p0c 2 /adc 2 p0c 1 /adc 1 p0c 0 /adc 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 gnd x in x out reset int p0f 0 /rls p0d 0 /sck p0d 2 /si p0d 3 /tm1out p0e 1 p0e 2 p0e 3 p0d 1 /so p0e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 m m m m m m pd17145ct(a1) - pd17145gt(a1) - pd17147ct(a1) - pd17147gt(a1) - pd17149ct(a1) - pd17149gt(a1) - 5 m pd17145(a1), 17147(a1), 17149(a1) block diagram notes 1. the rom capacity of each product is as follows: 1024 16 bits: m pd17145(a1) 2048 16 bits: m pd17147(a1) 4096 16 bits: m pd17149(a1) 2. the stack capacity of each product is as follows: 5 10 bits: m pd17145(a1) 5 11 bits: m pd17147(a1) 5 12 bits: m pd17149(a1) remark cmos or n-ch in ( ) indicate the output format of the port. cmos : cmos push-pull output n-ch : n-ch open-drain output v dd p0a 3 p0a 2 p0a 1 p0a 0 p0b 3 p0b 2 p0b 1 p0b 0 p0c 3 /adc 3 p0c 2 /adc 2 p0c 1 /adc 1 p0c 0 /adc 0 p0f 1 /v ref p0f 0 /rls p0d 3 /tm1out p0d 2 /si p0d 1 /so p0d 0 /sck tm1 serial interface p0d (n-ch) p0f a/d converter p0c (cmos) p0b (cmos) p0a (cmos) rf ram 110 4 bits system reg. alu rom note 1 program counter stack note 2 irqsio instruction decoder p0e (n-ch) timer 0 timer 1 basic interval timer interrupt controller clock divider system clock generator fx/2 n cpu clock clk stop x in x out int irqtm0 irqtm1 irqbtm irqsio irqbtm fx/2 n fx/2 n fx/2 n irqtm1 irqtm0 p0e 3 p0e 2 p0e 1 p0e 0 reset gnd 6 m pd17145(a1), 17147(a1), 17149(a1) contents 1. pin .......................................................................................................................... ........... 9 1.1. pin function ............................................................................................................................... ...... 9 1.2 equivalent circuit of pin ............................................................................................................... 11 1.3 handling of unused pins .............................................................................................................. 15 1.4 note on using reset and p0f 0 /rls pins ............................................................................... 16 2. program memory (rom) ...................................................................................... 17 2.1 configuration of program memory .............................................................................................. 17 3. program counter (pc) ....................................................................................... 18 3.1 configuration of program counter .............................................................................................. 18 3.2 operation of program counter .................................................................................................... 18 4. stack ........................................................................................................................... 19 4.1 configuration of stack .................................................................................................................. 19 4.2 stack function ............................................................................................................................... 19 5. data memory (ram) ............................................................................................... 20 5.1 configuration of data memory ..................................................................................................... 20 6. general register (gr) ........................................................................................ 21 6.1 general register pointer (rp) ..................................................................................................... 21 7. system register (sysreg) ................................................................................ 22 7.1 configuration of system register ............................................................................................... 22 8. register file (rf) .................................................................................................. 24 8.1 configuration of register file ...................................................................................................... 24 8.2 function of register file .............................................................................................................. 25 9. data buffer (dbf) ................................................................................................. 26 9.1 configuration of data buffer ........................................................................................................ 26 9.2 function of data buffer ................................................................................................................ 27 10. alu block .................................................................................................................. 28 10.1 configuration of alu block .......................................................................................................... 28 11. ports ........................................................................................................................... 30 11.1 port 0a (p0a 0 , p0a 1 , p0a 2 , p0a 3 ) .............................................................................................. 30 11.2 port 0b (p0b 0 , p0b 1 , p0b 2 , p0b 3 ) .............................................................................................. 31 11.3 port 0c (p0c 0 /adc 0 , p0c 1 /adc 1 , p0c 2 /adc 2 , p0c 3 /adc 3 ) ................................................... 32 11.4 port 0d (p0d 0 /sck, p0d 1 /so, p0d 2 /si, p0d 3 /tm1out) ........................................................ 33 11.5 port 0e (p0e 0 , p0e 1 , p0e 2 , p0e 3 ) .............................................................................................. 34 11.6 port 0f (p0f 0 /rls, p0f 1 /v ref ) ................................................................................................... 34 7 m pd17145(a1), 17147(a1), 17149(a1) 12. 8-bit timers/counters (tm0, tm1) ................................................................... 35 12.1 configuration of 8-bit timers/counters ..................................................................................... 35 13. basic interval timer (btm) ............................................................................... 39 13.1 configuration of basic interval timer ........................................................................................ 39 13.2 registers controlling basic interval timer ............................................................................... 41 13.3 watchdog timer function ........................................................................................................... 43 14. a/d converter ......................................................................................................... 45 14.1 configuration of a/d converter .................................................................................................. 45 14.2 function of a/d converter ........................................................................................................... 46 14.3 operation of a/d converter ........................................................................................................ 47 15. serial interface (sio) ......................................................................................... 50 15.1 function of serial interface ......................................................................................................... 50 15.2 operation mode of 3-wire serial interface ............................................................................... 52 16. interrupt function .............................................................................................. 54 16.1 types of interrupt causes and vector addresses ................................................................... 54 16.2 hardware of interrupt control circuit ......................................................................................... 55 17. standby function ................................................................................................. 56 17.1 outline of standby function ....................................................................................................... 56 17.2 halt mode ............................................................................................................................... .... 58 17.3 stop mode ............................................................................................................................... .... 60 18. reset ............................................................................................................................ 63 18.1 reset function .............................................................................................................................. 6 3 18.2 reset operation ........................................................................................................................... 64 19. poc circuit (mask option) ................................................................................. 65 19.1 function of poc circuit ............................................................................................................... 65 19.2 conditions to use poc circuit ................................................................................................... 66 20. instruction set ...................................................................................................... 67 20.1 outline of instruction set ............................................................................................................. 67 20.2 legend ............................................................................................................................... ............ 68 20.3 instruction set ............................................................................................................................... 69 20.4 assembler (as17k) embedded macro instruction ................................................................... 71 21. assembler reserved words ........................................................................... 72 21.1 mask option directive .................................................................................................................. 72 21.2 reserved symbols ....................................................................................................................... 74 22. electrical specifications ............................................................................... 82 23. characteristic curve (reference value) ............................................... 88 8 m pd17145(a1), 17147(a1), 17149(a1) 24. package drawings .................................................................................................... 90 25. recommended soldering conditions .............................................................. 94 appendix a. function comparison between m pd17145 subseries and the m pd17135a and 17137a ...................................................................... 96 appendix b. development tools ................................................................................. 98 9 m pd17145(a1), 17147(a1), 17149(a1) symbol v dd p0f 1 /v ref p0c 3 /adc 3 to p0c 0 /adc 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 p0e 3 p0e 2 p0e 1 p0e 0 p0d 3 /tm1out p0d 2 /si p0d 1 /so p0d 0 /sck 1. pin 1.1. pin function function power supply. reference voltage input to port 0f and a/d converter. pull-up resistor can be connected by mask option. p0f 1 bit 1 of 2-bit input port (p0f) v ref reference voltage input pin of a/d converter analog input to port 0c and a/d converter. p0c 3 -p0c 0 4-bit i/o port can be set in input or output mode bitwise. adc 3 -adc 0 analog inputs to a/d converter. port 0b. 4-bit i/o port can be set in input or output mode in 4-bit units. pull-up resistor can be connected in 4-bit units via software. port 0a. 4-bit i/o port. can be set in input or output mode in 4-bit units. pull-up resistor can be connected in 4-bit units via software. port 0e. 4-bit i/o port. can be set in input or output mode in 4-bit units. pull-up resistor can be connected in 4-bit units via software. port 0d that is also used for timer 1 output, serial data input, serial data output, and serial clock i/o. pull-up resistor can be connected bitwise via software. p0d 3 -p0d 0 4-bit i/o port. can be set in input or output mode bitwise. tm1out timer 1 output si serial data input so serial data output sck serial clock i/o output format ? input cmos push-pull cmos push-pull cmos push-pull n-ch open-drain n-ch open-drain after reset ? input (p0f 1 ) input (p0c) input input input input (p0d) pin number 1 2 3 to 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 10 m pd17145(a1), 17147(a1), 17149(a1) output format input input input ? ? after reset input (p0f 0 ) input input ? ? function port 0f or standby mode release signal input. pull-up resistor can be connected by mask option. r0f 0 bit 0 of 2-bit input port (p0f) rls standby mode release signal input external interrupt request signal input. also used to release standby mode. pull-up resistor can be connected by mask option. system reset input. pull-up resistor can be connected by mask option. for system clock oscillation. connect ceramic resonator across x in and x out . gnd symbol p0f 0 /rls int reset x out x in gnd pin number 23 24 25 26 27 28 11 m pd17145(a1), 17147(a1), 17149(a1) 1.2 equivalent circuit of pin the input/output circuit of each pin is shown below, partially simplified. (1) p0a 0 to p0a 3 and p0b 0 to p0b 3 data output disable pull-up flag v dd p-ch p-ch n-ch v dd output latch selector input buffer 12 m pd17145(a1), 17147(a1), 17149(a1) (2) p0c 0 /adc 0 to p0c 3 /adc 3 (3) p0d 3 /tm1out and p0d 1 /so data v dd p-ch n-ch output disable input disable output latch selector a/d converter input buffer pull-up flag p-ch v dd data output disable n-ch output latch selector input buffer 13 m pd17145(a1), 17147(a1), 17149(a1) (4) p0d 2 /si and p0d 0 /sck (5) p0e 0 to p0e 3 (6) p0f 0 /rls v dd p-ch pull-up flag n-ch output disable data output latch selector input buffer v dd data output disable n-ch p-ch pull-up flag output latch selector input buffer v dd stand-by release input buffer mask option 14 m pd17145(a1), 17147(a1), 17149(a1) (7) p0f 1 /v ref (8) reset and int v dd a/d end stop mode p-ch v ref a/d select input buffer mask option v dd input buffer mask option 15 m pd17145(a1), 17147(a1), 17149(a1) 1.3 handling of unused pins handle unused pins as shown in the table below. table 1-1. handling of unused pins handling pin name internally externally open connect to v dd via pull-up resistor, or to gnd via pull-down resistor note 1 . directly connect to v dd or gnd. open directly connect to gnd. directly connect to v dd or gnd. open directly connect to v dd . notes 1. take into consideration the drive capability and current dissipation of a port when the port is externally pulled up or down. to pull up or down the port with a high resistance, exercise care so that noise is not superimposed on the port pin. the appropriate value of the pull-up or pull- down resistor differs depending on the application circuit. generally, select a resistor of several 10 k w . 2. the p0f 0 /rls pin is also used to set a test mode. when this pin is not used, do not connect a pull-up resistor to it by mask option, but directly connect it to gnd. 3. in an application circuit where a high reliability is required, be sure to input the reset signal from an external source. the reset pin is also used to set a test mode. when this pin is not used, directly connect it to v dd . caution it is recommended to fix the input/output mode, pull-up resistor by software, and the output level of the pin by repeatedly setting them in each loop of the program. connect on-chip pull-up resistor via software. do not connect on-chip pull-up resistor by mask option. connect on-chip pull-up resistor by mask option. do not connect on-chip pull-up resistor by mask option. output low level. do not connect pull-up on-chip resistor via software, but output low level. connect on-chip pull-up resistor via software and output high level. do not connect on-chip pull-up resistor by mask option. connect on-chip pull-up resistor by mask option. do not connect on-chip pull-up resistor by mask option. connect on chip pull-up resistor by mask option. p0a, p0b, p0d, p0e p0c p0f 1 p0f 0 note 2 p0a, p0b, p0c (cmos port) p0d (n-ch open-drain port) p0e (n-ch open-drain port) external interrupt (int) reset note 3 (when only internal poc circuit is used) input mode output mode port open 16 m pd17145(a1), 17147(a1), 17149(a1) 1.4 note on using reset and p0f 0 /rls pins the reset and p0f 0 /rls pins also have a function to set a test mode in which the internal operation of the m pd17149(a1) is tested (for ic test only), in addition to the function described in 1.1 pin function . if a voltage higher than v dd is applied to these pins, the test mode is set. if a noise higher than v dd is superimposed on these pins during normal operation, therefore, the test mode is set by mistake, affecting normal operation. if the wiring length of the reset or p0f 0 /rls pin is too long, for example, noise may be superimposed on the pin. to prevent this, the wiring length must be kept as short as possible. otherwise, use a diode or capacitor as shown below. l l connect a low-v f diode between v dd l l connect a capacitor between v dd and reset, p0f 0 /rls and reset, p0f 0 /rls v dd v dd reset, p0f 0 /rls v dd v dd reset, p0f 0 /rls diode with low v f 17 m pd17145(a1), 17147(a1), 17149(a1) 2. program memory (rom) table 2-1 shows the program memory configuration of the m pd17145(a1), 17147(a1), and 17149(a1). table 2-1. program memory configuration part number program memory capacity program memory address m pd17145(a1) 2 kb (1024 16 bits) 0000h-03ffh m pd17147(a1) 4 kb (2048 16 bits) 0000h-07ffh m pd17149(a1) 8 kb (4096 16 bits) 0000h-0fffh the program memory stores programs and constant data tables. the program memory is addressed by the program counter. addresses 0000h-0005h are allocated to a reset start address and various interrupt vector addresses. 2.1 configuration of program memory figure 2-1 shows the program memory map. the program memory is divided in units called pages each of which consists of 2k steps with one step made up of 16 bits. addresses 0000h-07ffh (page 0) of the program memory can be specified by the direct subroutine call instruction. the entire address range of the program memory, 0000h-0fffh, can be specified by the branch, indirect subroutine call, and table reference instructions. figure 2-1. program memory map 0000h 0001h 0002h 0003h 0004h 0005h 03ffh 07ffh 0fffh (with pd17145(a1)) (with pd17147(a1)) (with pd17149(a1)) m m m address 16 bits reset start address serial interface interrupt vector basic interval timer interrupt vector timer 1 interrupt vector timer 0 interrupt vector external (int) interrupt vector page 0 call addr instruction subroutine entry address page 1 br addr instruction branch address br @ar instruction branch address call @ar instruction subroutine entry address movt dbf, @ar instruction table reference address 18 m pd17145(a1), 17147(a1), 17149(a1) 3. program counter (pc) the program counter is used to address the program memory. 3.1 configuration of program counter the program counter is a 10-/11-/12-bit binary counter as shown in figure 3-1. figure 3-1. program counter 3.2 operation of program counter usually, the contents of the program counter are automatically incremented each time an instruction has been executed. when reset has been effected, when a branch, subroutine call, return, or table reference instruction has been executed, or when an interrupt has been acknowledged, the address of the program memory to be executed next is set to the program counter. figure 3-2. value of program counter after instruction execution bit of program counter value of program counter instruction pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 at reset 000000 0000 00 0 1 value specified by addr call addr 0 br @ar call @ar contents of address register (ar) (movt dbf, @ar) ret retsk contents of address stack indicated by stack pointer (return address) reti when interrupt is acknowledged vector address of each interrupt remark the m pd17145(a1) does not have pc11 and pc10. the m pd17147(a1) does not have pc11. br addr msb pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc ( pd17145(a1)) pc ( pd17147(a1)) pc ( pd17149(a1)) lsb m m m 19 m pd17145(a1), 17147(a1), 17149(a1) 4. stack the stack is a register to which the return address of the program or the contents of the system registers, which are described later, are saved when a subroutine call instruction is executed or when an interrupt is acknowledged. 4.1 configuration of stack figure 4-1 shows the configuration of the stack. the stack consists of a 3-bit binary counter, stack pointer (sp), five 10-bit ( m pd17145(a1)), 11-bit ( m pd17147(a1)), or 12-bit ( m pd17149(a1)) address stack registers (asrs), and three 5-bit interrupt stack registers (intsks). figure 4-1. configuration of stack 4.2 stack function the stack is used to save a return address when the subroutine call or table reference instruction is executed. when an interrupt is acknowledged, the return address of the program and the contents of the program status word (psword) are automatically saved to the stack. after they are saved to the stack, all the bits of psword are cleared to 0. b 2 spb 2 b 1 spb 1 b 0 spb 0 0h 1h 2h 3h 4h b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 bcdsk0 bcdsk1 bcdsk2 cmpsk0 cmpsk1 cmpsk2 cysk0 cysk1 cysk2 zsk0 zsk1 zsk2 ixesk0 ixesk1 ixesk2 0h 1h 2h stack pointer (sp) sp is initialized to 5h at reset. address stack registers (asrs) address stack register 0 address stack register 1 address stack register 2 address stack register 3 address stack register 4 interrupt stack registers (intsks) 20 m pd17145(a1), 17147(a1), 17149(a1) 5. data memory (ram) the data memory is used to store data for operation and control. data can always be written to or read from this memory by using an instruction. 5.1 configuration of data memory the data memory is assigned addresses each consisting of 7 bits. the higher 3 bits of an address are called a row address, while the lower 4 bits are called a column address. take address 1ah for example. the row address of this address is 1h and the column address is 0ah. one address consists of 4 bits (= 1 nibble) of memory. the data memory consists of an area to which the user can save data, and areas to which special functions are allocated in advance. these areas are: system register (sysreg) (refer to 7. system register (sysreg).) data buffer (dbf) (refer to 9. data buffer (dbf).) port register (refer to 11. port.) figure 5-1. configuration of data memory 0123456789abcdef dbf3 dbf2 dbf1 dbf0 p0e (4 bits) p0f (2 bits) p0a (4 bits) p0b (4 bits) p0c (4 bits) p0d (4 bits) 0 1 2 3 4 5 6 7 bank0 example : address 1ah of bank0 system register column address 21 m pd17145(a1), 17147(a1), 17149(a1) 6. general register (gr) as its name implies, the general register is used for general purposes such as data transfer and operation. the general register of the 17k series is not a fixed area, but an area specified on the data memory by using the general register pointer (rp). therefore, a part of the data memory area can be specified as a general register as necessary, so that data can be transferred between data memory areas and the data in the data memory can be operated with a single instruction. 6.1 general register pointer (rp) rp is a pointer that specifies part of the data memory as the general register. rp specifies the bank and row addresses of a data memory area that is to be specified as the general register. consisting of a total of 7 bits, rp is assigned to 7dh (rph) and 7eh (rpl), and the higher 3 bits of the system register (refer to 7. system register (sysreg ) ). rph specifies a bank, and rpl specifies a data memory row address. figure 6-1. configuration of general register pointer bank0 rp 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 2 3 4 5 6 7 7dh 7eh rph rpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0000 d 0000000 c b 0 row addresses 0h to 7h can be specified by general register pointer (rp). row address column address system register general register area when rph = 0000b, rpl = 010 b address name symbol bit data reset general register pointer (rp) general register (16 nibbles) general register (16 nibbles) 22 m pd17145(a1), 17147(a1), 17149(a1) 7. system register (sysreg) the system register (sysreg) is a register that directly controls the cpu, and is located on the data memory. 7.1 configuration of system register figure 7-1 shows the location of the system register on the data memory. as shown in this figure, the system register is located at addresses 74h-7fh of the data memory. because the system register is located on the data memory, it can be manipulated by all the data memory manipulation instructions. it is therefore possible to specify the system register as a general register. figure 7-1. location of system register on data memory figure 7-2 shows the configuration of the system register. as shown in this figure, the system register consists of the following seven registers: address register (ar) window register (wr) bank register (bank) index register (ix) data memory row address pointer (mp) general register pointer (rp) program status word (psword) 0123456789abcdef 0 1 2 3 4 5 6 7 456789abcdef 0123 data memory (bank0) column address row address port register system register (sysreg) 23 m pd17145(a1), 17147(a1), 17149(a1) figure 7-2. configuration of system register notes 1. 0 in this field means that the bit is fixed to 0. 2. b 3 and b 2 of ar2 of the m pd17145(a1) are fixed to 0. b 3 of ar2 of the m pd17147(a1) is fixed to 0. 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh ar3 ar2 ar1 ar0 wr bank ixh ixm ixl rph rpl psw mph mpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0000000000000000 0000000000000000000000000000 000 0000 0000 0000 (rp) (mp) (ix) (bank) (ar) m p e b c d c m p c yz i x e address name symbol bit data note1 initial value at reset 0 note2 undefi- ned address register (ar) window register (wr) bank register (bank) index register (ix) data memory row address pointer (mp) general register pointer (rp) program status word (psword) 24 m pd17145(a1), 17147(a1), 17149(a1) 8. register file (rf) the register file is a register that mainly sets the conditions of the peripheral hardware. 8.1 configuration of register file 8.1.1 configuration of register file figure 8-1 shows the configuration of the register file. as shown in this figure, the register file consists of 128 nibbles (128 4 bits). like the data memory, the register file is assigned addresses in 4-bit units, with row addresses 0h-7h and column addresses 0h-0fh. addresses 00h-3fh of the register file are called a control register. figure 8-1. configuration of register file 8.1.2 register file and data memory figure 8-2 shows the relationships between the register file and data memory. as shown in this figure, addresses 40h to 7fh of the register file overlaps the data memory. it seems from the program as if addresses 40h to 7fh of the data memory exist at addresses 40h-7fh of the register file. 0123456789abcdef 0 1 2 3 4 5 6 7 control register row address column address register file 25 m pd17145(a1), 17147(a1), 17149(a1) figure 8-2. relationships between register file and data memory 8.2 function of register file 8.2.1 function of register file the register file is a collection of registers that set the conditions of the peripheral hardware by using the peek or poke instruction. the registers that control the peripheral hardware are allocated to addresses 00h-3fh. these registers are called control registers. addresses 40h-7fh of the register file overlap the ordinary data memory. these addresses can therefore be read or written by not only the mov instruction but also the peek and poke instructions. 8.2.2 functions of control registers the control registers are used to set the conditions of the peripheral hardware listed below. for the details of the peripheral hardware and control registers, refer to the description of each peripheral hardware. port 8-bit timers/counters (tm0, tm1) basic interval timer (btm) a/d converter serial interface (sio) interrupt function stack pointer (sp) 0 1 2 3 0 1 2 3 4 5 7 6 0123456789abcdef bank0 column address data memory port register system register control register register file row address 26 m pd17145(a1), 17147(a1), 17149(a1) 9. data buffer (dbf) the data buffer consists of 4 nibbles allocated to addresses 0ch-0fh of bank0 of the data memory. this area is a data storage area that transfers data with the peripheral hardware of the cpu (address register, serial interface, timers 0 and 1, and a/d converter) by using the get or put instruction. moreover, the constants on the program memory can be read to the data buffer by using the movt dbf, @ar instruction. 9.1 configuration of data buffer figure 9-1 shows the location of the data buffer on the data memory. as shown in this figure, the data buffer is allocated addresses 0ch-0fh of the data memory, and consists of a total of 16 bits or 4 nibbles (4 4 bits). figure 9-1. location of data buffer figure 9-2 shows the configuration of the data buffer. as shown in this figure, the data buffer consists of 16 bits of the data memory, with the bit 0 of address 0fh as the lsb and bit 3 of address 0ch as the msb. figure 9-2. configuration of data buffer because the data buffer is located on the data memory, it can be manipulated by all the data memory manipulation instructions. 0 f 123456789abcde 0 1 2 3 4 5 6 7 data memory bank0 column address data buffer (dbf) system register (sysreg) row address data memory bank0 0ch 0dh 0eh 0fh b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 15 b 14 b 13 b 12 dbf3 dbf2 dbf1 dbf0 m s b < > l s b < < address bit bit symbol data data data buffer 27 m pd17145(a1), 17147(a1), 17149(a1) 9.2 function of data buffer the data buffer has two main functions. one is to transfer data with the peripheral hardware, and the other is to read the constant data on the program memory (table reference). figure 9-3 shows the relationships between the data buffer and peripheral hardware. figure 9-3. data buffer and peripheral hardware 01h 02h 03h 04h 40h 45h shift register (siosfr) timer 0 modulo register (tm0m) timer 1 modulo register (tm1m) a/d converter data register (adcr) address register (ar) timer 0 timer 1 count register (tm0tm1c) data buffer (dbf) internal bus program memory (rom) constant data peripheral address peripheral hardware 28 m pd17145(a1), 17147(a1), 17149(a1) 10. alu block the alu executes arithmetic and logical operations, bit judgment, and rotation processing of 4-bit data. 10.1 configuration of alu block figure 10-1 shows the configuration of the alu block. as shown, the alu block consists of an alu that processes 4-bit data, and peripheral circuits such as temporary registers a and b, status flip-flops that control the status of the alu, and a decimal adjustment circuit that is used when a bcd operation is performed. the status flip-flops are a zero flag ff, carry flag ff, compare flag ff, and bcd flag ff, as shown in figure 10-1. the status flip-flops correspond to the zero flag (z), carry flag (cy), compare flag (cmp), and bcd flag (bcd) of the program status word (psword: addresses 7eh, 7fh) on a one-to-one basis. 29 m pd17145(a1), 17147(a1), 17149(a1) figure 10-1. configuration of alu block alu 7eh 7fh program status word (psword) b 0 b 3 b 2 b 1 b 0 bcd cmp cy z ixe bcd flag ff cmp flag ff cy flag ff z flag ff data bus status flip-flop temporary register b temporary register a arithmetic operation logical operation bit judgment compare judgment rotation processing decimal adjustment circuit address name bit flag status flip-flop functional outline indicates that result of arithmetic operation is 0. stores carry or borrow resulting from arithmetic operation. specifies whether result of arithmetic operation is stored. specifies whether decimal adjustment is performed when arithmetic operation is executed. 30 m pd17145(a1), 17147(a1), 17149(a1) 11. ports 11.1 port 0a (p0a 0 , p0a 1 , p0a 2 , p0a 3 ) port 0a is a 4-bit i/o port with an output latch. it is mapped at address 70h of bank0 of the data memory. the output format is cmos push-pull output. this port can be set in the input or output mode in 4-bit units. the input or output mode is specified by p0agio (bit 0 of address 2ch) on the register file. when p0agio = 0, all the pins of port 0a are set in the input mode. when an instruction that reads the data of the port register is executed at this time, the pin status is read. when p0agio = 1, all the pins of port 0a are set in the output mode, and the contents written to the output latch are output to the pins. when an instruction that reads the port status is executed with the port set in the output mode, the contents of the output latch, instead of the pin status, are read. a pull-up resistor can be connected on-chip to this port through software. whether the pull-up resistor is connected is specified by p0agpu (bit 0 at address 0ch) of the register file. all the four pins are pulled up when p0agpu = 1. when p0agpu = 0, the pull-up resistor is not connected. p0agio and p0agpu are cleared to 0 at reset, and all the p0a pins are set in the input mode without the pull-up resistor connected. the value of the output latch is also cleared to 0. table 11-1. writing and reading port register (0.70h) p0agio input/output bank0 70h rf: 2ch, bit 0 mode of pin write read 0 input enabled p0a pin status 1 output write to p0a latch p0a latch contents 31 m pd17145(a1), 17147(a1), 17149(a1) 11.2 port 0b (p0b 0 , p0b 1 , p0b 2 , p0b 3 ) port 0b is a 4-bit i/o port with an output latch. it is mapped at address 71h of bank0 of the data memory. the output format is cmos push-pull output. this port can be set in the input or output mode in 4-bit units. the input or output mode is specified by p0bgio (bit 1 of address 2ch) on the register file. when p0bgio = 0, all the pins of port 0b are set in the input mode. when an instruction that reads the data of the port register is executed at this time, the pin status is read. when p0bgio = 1, all the pins of port 0b are set in the output mode, and the contents written to the output latch are output to the pins. when an instruction that reads the port status is executed with the port set in the output mode, the contents of the output latch, instead of the pin status, are read. a pull-up resistor can be connected on-chip to this port through software. whether the pull-up resistor is connected is specified by p0bgpu (bit 1 at address 0ch) of the register file. all the four-bit pins are pulled up when p0bgpu = 1. when p0bgpu = 0, the pull-up resistor is not connected. p0bgio and p0bgpu are cleared to 0 at reset, and all the p0b pins are set in the input mode without the pull-up resistor connected. the value of the output latch is also cleared to 0. table 11-2. writing and reading port register (0.71h) p0bgio input/output bank0 71h rf: 2ch, bit 1 mode of pin write read 0 input enabled p0b pin status 1 output write to p0b latch p0b latch contents 32 m pd17145(a1), 17147(a1), 17149(a1) 11.3 port 0c (p0c 0 /adc 0 , p0c 1 /adc 1 , p0c 2 /adc 2 , p0c 3 /adc 3 ) port 0c is a 4-bit i/o port with an output latch. it is mapped at address 72h of bank0 of the data memory. the output format is cmos push-pull output. this port can be set in the input or output mode in 1-bit units. the input or output mode is specified by p0cbio0-p0cbio3 (address 1ch) on the register file. when p0cbion = 0 (n = 0 to 3), the corresponding port pin, p0cn, is set in the input mode. when an instruction that reads the data of the port register is executed at this time, the pin status is read. when p0cbion = 1 (n = 0 to 3), the p0cn pin is set in the output mode, and the contents written to the output latch are output to the pin. when an instruction that reads the port status is executed with a port pin set in the output mode, the contents of the output latch, instead of the pin status, are read. at reset, p0cbio0-p0cbio3 are cleared to 0, setting all the p0c pins in the input mode. the contents of the output latch are also cleared to 0 at this time. port 0c is also used to input analog voltages to the a/d converter. whether each pin of the port is used as a port pin or analog input pin is specified by p0c0idi-p0c3idi (address 1bh) on the register file. when p0cnidi = 0 (n = 0-3), the p0c n /adc n pin functions as a port pin. when p0cnidi = 1 (n = 0 to 3), the p0c n /adc n pin functions as an analog input pin of the a/d converter. if any of the p0cnidi (n = 0 to 3) bits is set to 1, the p0f 1 /v ref pin is used as the v ref pin. when a pin of port 0c is used as an analog input pin of the a/d converter, set the p0cnidi corresponding to the pin to which an analog voltage is applied to 1, to disable the port input function. moreover, clear p0cbion (n = 0-3) to 0 to set the input port mode. the pin used as an analog input pin is selected by adcch0 and adcch1 (bits 1 and 0 of address 22h) on the register file. at reset, p0cbio0-p0cbio3, p0c0idi-p0c3idi, adcch0, and adcch1 are cleared to 0, setting the input port mode. table 11-3. selecting port or a/d converter mode (n = 0 to 3) p0cnidi p0cbion bank0 72h function rf:1bh rf:1ch write read 0 input port enabled. p0c latch pin status 1 port output enabled. p0c latch contents of p0c latch 0 analog input of a/d note 1 enabled. p0c latch contents of p0c latch 1 output port and analog 1 enabled. p0c latch contents of p0c latch input of a/d note 2 notes 1. normal setting when the p0c pins are used as the analog input pins of the a/d converter. 2. the p0c pins function as output port pins. at this time, the analog input voltages change with the output from the port. to use the pins as analog input pins, be sure to clear p0cbion to 0. 0 33 m pd17145(a1), 17147(a1), 17149(a1) 11.4 port 0d (p0d 0 /sck, p0d 1 /so, p0d 2 /si, p0d 3 /tm1out) port 0d is a 4-bit i/o port with an output latch. it is mapped at address 73h of bank0 of the data memory. the output format is n-ch open-drain output. this port can be set in the input or output mode in 1-bit units. the input or output mode is specified by p0dbio0-p0dbio3 (address 2bh) on the register file. when p0dbion = 0 (n = 0 to 3), the corresponding port pin, p0dn, is set in the input mode. when an instruction that reads the data of the port register is executed at this time, the pin status is read. when p0dbion = 1, the p0dn pin is set in the output mode, and the contents written to the output latch are output to the pin. when an instruction that reads the port status is executed with a port pin set in the output mode, the contents of the output latch, instead of the pin status, are read. a pull-up resistor can be connected on-chip to this port through software. whether the pull-up resistor is connected or not is specified bitwise by using p0dbpu0-p0dbpu3 (address 0dh) on the register file. when p0dbpun = 1, the p0dn pin is pulled up. when p0dbpun = 0, the pull-up resistor is not connected. at reset, p0dbion is cleared to 0, setting all the p0d pins in the input mode. the contents of the output latch are also cleared to 0 at this time. note that the contents of the output latch are not changed even if the status of p0dbion is changed from 1 to 0. port 0d is also used as serial interface input/output and timer 1 output pins. whether the p0d 0 to p0d 2 pins are used as port pins or serial interface i/o pins (sck, so, and si) is specified by sioen (bit 0 of 0bh) on the register file. whether the p0d 3 pin is used as a port pin or timer 1 output (tm1out) pin is specified by tm1osel (bit 3 of 0bh) on the register file. if tm1osel = 1, 1 is output when timer 1 is reset, and the output is inverted each time the count value of timer 1 coincides with the contents of the modulo register. table 11-4. contents of register file and pin function (n = 0 to 3) value of register file pin function tm1osel sioen p0dbion rf: 0bh rf: 0bh rf: 2bh p0d 0 /sck p0d 1 /so p0d 2 /si p0d 3 /tm1out bit 3 bit 0 bit n 0 input port 1 output port 0 input port 1 output port 0 input port 1 output port 0 1 sck so si sck so si tm1out 0 0 1 0 1 1 34 m pd17145(a1), 17147(a1), 17149(a1) table 11-5. read contents of port register (0.73h) port mode read contents of port register (0.73h) input port pin status output port contents of output latch internal clock selected as serial clock contents of output latch external clock selected as serial clock pin status si pin status so contents of output latch tm1out contents of output latch 11.5 port 0e (p0e 0 , p0e 1 , p0e 2 , p0e 3 ) port 0e is a 4-bit i/o port with an output latch. it is mapped at address 6eh of bank0 of the data memory. the output format is n-ch open-drain output. this port can be set in the input or output mode in 4-bit units. the input or output mode is specified by p0egio (bit 2 of address 2ch) on the register file. when p0egio = 0, all the pins of port 0e are set in the input mode. when an instruction that reads the data of the port register is executed at this time, the pin status is read. when p0egio = 1, all the pins of port 0e are set in the output port, and the contents written to the output latch are output to the pins. when an instruction that reads the port status is executed with the port set in the output mode, the contents of the output latch, instead of the pin status, are read. a pull-up resistor can be connected on-chip to this port through software. whether the pull-up resistor is connected is specified by p0egpu (bit 2 at address 0ch) of the register file. all the four-bit pins are pulled up when p0egpu = 1. when p0egpu = 0, the pull-up resistor is not connected. p0egio is cleared to 0 at reset, and all the p0e pins are set in the input mode. the value of the output latch is also cleared to 0. table 11-6. writing and reading port register (0.6eh) (n = 0 to 3) p0egio input/output bank0 6eh rf: 2ch, bit 2 mode of pin write read 0 input enabled p0e pin status 1 output write to p0e latch p0e latch contents 11.6 port 0f (p0f 0 /rls, p0f 1 /v ref ) port 0f is a 2-bit input port and mapped at address 6fh of bank0 of the data memory. a pull-up resistor can be connected on-chip bitwise to this port by mask option. if a read instruction that reads the port register is executed when both pins of port 0f are used as input port pins, the higher 2 bits of the register are fixed to 0, and the pin statuses are read to the lower 2 bits. executing a write instruction is meaningless as the contents of the port register remain unchanged. the p0f 0 /rls pin is also used to input a standby mode release signal. the p0f 1 /v ref pin inputs a reference voltage to the a/d converter when even one of the bits of p0cnidi (rf: address 1bh, n = 0 to 3) is set to 1. if an instruction is executed to read the port register when the p0f 1 /v ref pin functions as the v ref pin, bit 1 of address 6fh is always cleared to 0. sck 35 m pd17145(a1), 17147(a1), 17149(a1) 12. 8-bit timers/counters (tm0, tm1) the m pd17149(a1) is provided with two 8-bit timers/counters: timer 0 (tm0) and timer 1 (tm1). by using the count-up signal of timer 0 as the count pulse to timer 1, the two 8-bit timers can be used as a 16-bit timer. each timer is controlled through hardware manipulation by using the put or get instruction or manipulation of the registers on the register file by using the peek or poke instruction. 12.1 configuration of 8-bit timers/counters figure 12-1 shows the configuration of the 8-bit timers/counters. an 8-bit timer/counter consists of an 8-bit count register, an 8-bit modulo register, a comparator that compares the value of the count register with that of the modulo register, and a selector that selects the count pulse. cautions 1. the modulo register is a write register. 2. the count register is a read register. 36 m pd17145(a1), 17147(a1), 17149(a1) figure 12-1. configuration of 8-bit timer/counter data buffer (dbf) int tm0en tm0res tm0ck1 tm0ck0 2 int dq clk r tm1osel p0dbio3 p0d 3 / tm1out tm1out ff dq clk r 2 tm1en tm1res tm1ck1 tm1ck0 internal bus interrupt control register (rf:0fh) timer 0 mode register (rf:11h) selector system clock/16 system clock/512 system clock/64 latch reset clear timer 0 modulo register (8) (tm0m) timer 0 comparator (8) timer 0 count register (8) (tm0c) coincidence timer 0 count-up signal (to timer 1) irqtm0 set signal irqtm0 clear signal internal reset data buffer (dbf) internal bus system clock/128 latch reset timer 1 modulo register (8) (tm1m) timer 1 comparator (8) timer 1 count register (8) (tm1c) timer 1 mode register (rf:12h) coincidence reset irqtm1 set signal irqtm1 clear signal clear system clock/8192 system clock/16 timer 0 count up selector internal reset serial interface control register (rf:0bh) port control register of bit i/o (rf:2bh) p0db 3 output latch 37 m pd17145(a1), 17147(a1), 17149(a1) figure 12-2. timer 0 mode register rf : 11h bit 3 tm0en 0 bit 2 tm0res 0 bit 1 tm0ck1 0 bit 0 tm0ck0 0 r/w tm0ck1 0 0 1 1 tm0ck0 0 1 0 1 tm0res 0 1 tm0en 0 1 read/write initial value at reset read = r, write = w selects count pulse of timer 0 system clock/16 system clock/512 system clock/64 int pin resets timer 0 resets timer 0 count register and irqtm0 does not affect timer 0 remark tm0res is automatically cleared to 0 after it has been set to 1. when it is read, "0" is always read. timer 0 start command resumes counting of timer 0 stops counting of timer 0 remark tm0en can be used as a status flag that detects the count status of timer 0 (1 : counting in progress, 0 : counting stopped) 38 m pd17145(a1), 17147(a1), 17149(a1) figure 12-3. timer 1 mode register rf : 12h bit 3 tm1en 1 r/w bit 2 tm1res 0 bit 1 tm1ck1 0 bit 0 tm1ck0 0 tm1ck1 0 0 1 tm1ck0 0 1 0 tm1res 0 11 1 tm1en 0 1 read/write initial value at reset selects count pulse of timer 1 system clock/128 system clock/8192 system clock/16 resets timer 1 resets timer 1 count register and irqtm1 does not affect timer 1 remark tm1res is automatically cleared to 0 after it has been set to 1. when it is read, "0" is always read. timer 1 start command resumes counting of timer 1 stops counting of timer 1 remark tm1en can be used as a status flag that detects the count status of timer 1 (1 : counting in progress, 0 : countin g stopped ) count-up signal from timer 0 39 m pd17145(a1), 17147(a1), 17149(a1) 13. basic interval timer (btm) the m pd17149(a1) is provided with a 7-bit basic interval timer. this timer has the following functions: (1) generates reference time. (2) selects and counts wait time when standby mode is released. (3) watchdog timer function to detect program runaway. 13.1 configuration of basic interval timer figure 13-1 shows the configuration of the basic interval timer. 40 m pd17145(a1), 17147(a1), 17149(a1) figure 13-1. configuration of basic interval timer remark (1) to (4) in the figure correspond to the signals in the timing chart in figure 13-4. btm mode register (rf:13h) watchdog timer mode register (rf:13h) btmisel btmres btmck1 btmck0 wdtres 0 0 wdten 2 reset selector system clock/16384 system clock/4096 system clock/512 system clock/16 basic interval timer (7-bit divider) irqbtm set signal reset signal r s outputs "1" while counting 0 to 7 during counting from 0 to 255. f btm 2 7 f btm 2 5 f btm q 1-bit divider 1-shot pulse generator reset internal bus (1) (3) (4) (2) selector 41 m pd17145(a1), 17147(a1), 17149(a1) 13.2 registers controlling basic interval timer the basic interval timer is controlled by the btm mode register and watchdog timer mode register. figures 13-2 and 13-3 show the configuration of each register. figure 13-2. btm mode register selects count pulse to btm system clock/16 (1 instruction execution time) system clock/16384 (1024 instruction execution time) system clock/4096 (256 instruction execution time) system clock/512 (32 instruction execution time) btmck1 0 0 1 1 btmck0 0 1 0 1 resets btm does not affect basic interval timer (btm) resets binary counter of basic interval timer (btm) btmres 0 1 selects interval timer sets interval timer to 1/128 of count pulse sets interval timer to 1/32 of count pulse btmisel 0 1 remark read = r, write = w rf : 13h bit 3 btmisel 0 bit 2 btmres 0 bit 1 btmck1 0 bit 0 btmck0 0 btmres is automatically cleared to 0 after it has been set to 1. when it is read, "0" is always read. read/write initial value at reset r/w 42 m pd17145(a1), 17147(a1), 17149(a1) figure 13-3. watchdog timer mode register read = r, write = w rf : 03h enable watchdog timer stops watchdog timer. starts watchdog timer. wdten 0 1 resets watchdog timer does not affect watchdog timer. resets flip-flop that retains overflow carry of btm used for watchdog timer. wdtres 0 1 r/w remark 1. 2. wdten cannot be cleared to 0 by program. wdten is automatically cleared to 0 after it has been set to 1. when it is read, "0" is always read. read/write initial value at reset bit 3 wdtres 0 bit 2 0 0 bit 1 0 0 bit 0 wdten 0 remark wdtres is automatically cleared to 0 after it has been set to 1. when it is read, "0" is alwa y s read. 43 m pd17145(a1), 17147(a1), 17149(a1) 13.3 watchdog timer function the basic interval timer can also be used as a watchdog timer that detects a program runaway. 13.3.1 function of watchdog timer the watchdog timer is a counter that generates a reset signal at fixed time intervals. by inhibiting generation of this reset signal by program, the system can be reset (started from address 0000h) if the system becomes runaway due to external noise (if the watchdog timer is not reset within specific time). this function allows the program to escape from the runaway status because a reset signal is generated at fixed time intervals even when the program jumps to an unexpected routine and enters an indefinite loop due to external noise. 13.3.2 operation of watchdog timer when wdten is set to 1, the 1-bit divider is enabled to operate, and the basic interval timer starts operating as an 8-bit watchdog timer. once the watchdog timer has been started, it cannot be stopped until the device is reset and wdten is cleared to 0. reset effected by the watchdog timer can be inhibited in the following two ways: (1) repeatedly set wdtres in the program. (2) repeatedly set btmres in the program. in the case of (1), wdtres must be set while the count value of the watchdog timer is 8 to 191 (before it reaches 192). therefore, program so that set1 wdtres is executed at least once in a cycle shorter than that in which the watchdog timer counts 184. in the case of (2), btmres must be set before the basic interval timer (btm) counts 128. therefore, program so that set1 btmres is executed at least once in a cycle shorter than that in which btm counts 128. in this case, however, interrupts cannot be processed with btm. caution btm is not reset even if wdten is set. therefore, before setting wdten first, be sure to set btmres to reset btm. example set1 btmres set2 wdten, wdtres 44 m pd17145(a1), 17147(a1), 17149(a1) figure 13-4. timing chart of watchdog timer (when wdtres flag is used) wdten wdtres (4) f btm /2 8 (3) watchdog reset signal (active high) wdtres acknowledge period wdtres acknowledge period wdtres acknowledge period count value of watchdog timer 0 8 128 192 255 8 128 192 255 255 192 192 128 128 8 64 00 0 1-shot pulse generator output (1) f btm /2 7 (2) ( irqbtm set) reset signal is not generated 45 m pd17145(a1), 17147(a1), 17149(a1) 14. a/d converter the m pd17149(a1) is provided with an a/d converter with 4 analog input channels (p0c 0 /adc 0 -p0c 3 /adc 3 ) and a resolution of 8 bits. this a/d converter is of the successive approximation type and operates in the following two modes: 1 successive mode in which 8-bit a/d conversion is sequentially performed starting from the most significant bit 2 single mode in which an input analog voltage is compared with the set value of an 8-bit data register 14.1 configuration of a/d converter figure 14-1 shows the configuration of the a/d converter. figure 14-1. block diagram of a/d converter note the 8-bit data register (adcr) is cleared to 00h when the stop instruction is executed. internal bus read signal p0cn/adcn rf: 22h rf: 20h rf: 21h 0 0 adcch1 adcch0 0 0 0 adcstrt adcsoft 0 adccmp adcend control circuit comparator selector tap decoder 8-bit data register note (adcr) 8 8 d/a converter r/2 r r 3r/2 remark n = 0 to 3 output latch 4 selector p0cnidi p0cbion p0f 1 input data a/d end signal stop instruction signal p0f 1 /v ref p0cnidi 4 46 m pd17145(a1), 17147(a1), 17149(a1) 14.2 function of a/d converter (1) adc 0 to adc 3 pins these pins input analog voltages to the four channels of the a/d converter. the analog voltages are converted into digital signals. the a/d converter is provided with a sample and hold circuit, and an analog input voltage being converted into a digital signal is internally held. (2) v ref pin this pin inputs a reference voltage to the a/d converter. the signals input to adc 0 to adc 3 are converted into digital signals based on the voltage applied across v ref and gnd. the a/d converter of the m pd17149(a1) has a function to automatically stop the current flowing into the v ref pin when the a/d converter does not operate. a current flows into the v ref pin in the following cases: 1 in successive mode (adcsoft = 0) since the adcstrt flag has been set to 1 until the adcend flag is set to 1. 2 in single mode (adcsoft = 1) since the adcstrt flag has been set to 1 or a value has been written to the 8-bit data register until the result of comparison by the comparator is written to the adccmp flag. remarks 1. if the halt instruction is executed during a/d conversion, the a/d converter operates, in the successive mode, until the adcend flag is set, or in the single mode, until the result of conversion is stored to the adccmp flag. therefore, a current flows to the v ref pin during this period. 2. a/d conversion in progress is stopped if the stop instruction is executed. in this case, the a/d converter is initialized, and the current flowing to the v ref pin is cut (the a/d converter does not operate even if the stop mode has been released). (3) 8-bit data register (adcr) this is an 8-bit register that stores the result of a/d conversion of successive approximation type in the successive mode. the contents of this register are read by using the get instruction. in the single mode, the contents of the 8-bit data register are converted into an analog voltage by an internal d/a converter and is compared by the comparator with an analog signal input from the adcn pin. a value can be written to this register by using the put instruction. (4) comparator the comparator compares the analog input voltage with the voltage output by the d/a converter. if the analog input voltage is high, it outputs 1; if the voltage is low, the comparator outputs 0. the result of comparison is stored to the 8-bit data register (adcr) in the successive mode, and to the adccmp flag in the single mode. 47 m pd17145(a1), 17147(a1), 17149(a1) 14.3 operation of a/d converter the operation of the a/d converter can be executed in two modes, depending on the setting of the adcsoft flag: successive and single modes. adcsoft operation mode of a/d converter 0 successive mode (a/d conversion) 1 single mode (compare operation) figure 14-2. relationships between analog input voltage and digital conversion result n 256 ideal conversion result ffh feh fdh n 03h 02h 01h 00h digital conversion result 1 256 255 256 256 256 ( v dd ) analo g input volta g e ( v ) 0 2 256 254 256 48 m pd17145(a1), 17147(a1), 17149(a1) (1) timing in successive mode (a/d conversion) figure 14-3. timing in successive mode (a/d conversion) caution sampling is performed eight times while a/d conversion is executed once. if the analog input voltage changes heavily during a/d conversion, a/d conversion cannot be performed accurately. to obtain an accurate conversion result, it is necessary to minimize the changes in the analog input voltage during a/d conversion. remark one sampling time = 14/f x (1.75 m s, at 8 mhz) sampling repeat cycle = 48/f x (6 m s, at 8 mhz) sampling capacitor capacitance = 100 pf (max.) sampling sampling sampling adcstrt executed adcr read ? number of executed instructions (instruction cycle) adcstrt adcend 8-bit data register previous data initial value:80h highest 1 bit determined all 8 bits determined poke 123456789 24get highest 2 bits determined 49 m pd17145(a1), 17147(a1), 17149(a1) (2) timing in single mode (compare operation) figure 14-4. timing in single mode (compare operation) after 1 has been written to adcstrt in the single mode (execution of the poke instruction), a value is stored to adccmp three instructions after, and the result of comparison can be read by the peek instruction. even if data is set to adcr (execution of the put instruction), comparison is started in the same manner as adcstrt, and the result of comparison can be read three instructions after. the adccmp flag is cleared to 0 when reset is executed or when an instruction that writes data to adcr is executed. caution be sure to set adcsoft to 1 before setting a value to adcr. when adcsoft = 0, no value can be set to adcr (the put adcr, dbf instruction is invalidated). remark sampling time = 14/f x (1.75 m s, at 8 mhz) sampling capacitor capacitance = 100 pf (max.) sampling sampling poke peek put peek 12 12 adcstrt adcend adccmp adcstrt executed number of executed instructions (instruction cycle) previous data comparison result comparison result adccmp read adccmp read 50 m pd17145(a1), 17147(a1), 17149(a1) 15. serial interface (sio) the serial interface of the m pd17149(a1) consists of an 8-bit shift register (siosfr), a serial mode register, and a serial clock counter, and is used to input/output serial data. 15.1 function of serial interface the serial interface can transmit or receive 8-bit data in synchronization with the clock by using three wires: serial clock input (sck), serial data output (so), and serial data input (si) pins. this serial interface can connect various peripheral i/o devices in a mode compatible with the method employed for the m pd7500 series and 75x series. (1) serial clock four types of serial clocks, three internal and one external, can be selected. if an internal clock is selected as the serial clock, the selected clock is automatically output to the p0d 0 /sck pin. table 15-1. serial clocks siock1 siock0 selected serial clock 0 0 external clock from sck pin 0 1 system clock/16 1 0 system clock/128 1 1 system clock/1024 (2) transfer operation each pin of port 0d (p0d 0 /sck, p0d 1 /so, p0d 2 /si) functions as a serial interface pin when sioen is set to 1. if siots is set to 1 at this time, the serial interface starts its operation in synchronization with the falling edge of the external or internal clock. if siots is set, irqsio is automatically cleared. data is transferred starting from the most significant bit of the shift register in synchronization with the rising edge of the serial clock, and the information on the si pin is stored to the shift register, starting from the least significant bit, in synchronization with the rising edge of the serial clock. when 8-bit data has been completely transferred, siots is automatically cleared, and irqsio is set. remark when serial transfer is executed, transfer is started only from the most significant bit of the contents of the shift register. in other words, transfer cannot be started from the least significant bit. the status of the si pin is always loaded to the shift register in synchronization with the rising edge of the serial clock. 51 m pd17145(a1), 17147(a1), 17149(a1) figure 15-1. block diagram of serial interface caution the output latch of the shift register is independent of the output latch of p0d 1 . therefore, even if an output instruction is executed to p0d 1 , the status of the output latch of the shift register is not affected. the output latch of the shift register is cleared to 0 by reset input. after that, it holds the status of the lsb of the previously transferred data. p0d 2 /si p0d 1 /so p0d 0 /sck shift register (siosfr) p0d 1 output latch serial clock counter clear selector siots siohiz siock1 siock0 irqsio clear signal irqsio set signal one shot f x /1024 f x /128 f x /16 sioen p0dbio0 p0dbio1 q s r output latch lsb msb clock carry p0d 0 output latch selector serial start selector 52 m pd17145(a1), 17147(a1), 17149(a1) 15.2 operation mode of 3-wire serial interface the serial interface can operate in the following two modes. when the serial interface function is selected, the p0d 2 /si pin always inputs data in synchronization with the serial clock. 8-bit transmission/reception mode (simultaneous transmission/reception) 8-bit reception mode (so pin: high-impedance state) table 15-2. operation modes of serial interface sioen siohiz p0d 0 /si pin p0d 1 /so pin operation mode of serial interface 1 0 si so 8-bit transmission/reception mode 1 1 si p0d 1 (input) 8-bit reception mode 0 p0d 0 (i/o) p0d 1 (i/o) general-purpose port mode : don't care (1) 8-bit transmission/reception mode (simultaneous transmission/reception) input or output of serial data is controlled by the serial clock. the msb of the shift register is output to the so line at the falling edge of the serial clock (sck pin signal). the contents of the shift register are shifted 1 bit at the rising edge of the serial clock. at the same time, the data on the si line is loaded to the lsb of the shift register. the serial clock counter (3-bit counter) sets an interrupt request flag (irqsio <- 1) each time it has counted eight serial clocks. figure 15-2. timing in 8-bit transmission/reception mode (simultaneous transmission/reception) remark di: serial data input do: serial data output 12345678 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 do0 di0 sck pin si pin so pin irqsio starts transfer in synchronization with falling of sck pin executes instruction that writes "1" to siots ( transfer start command ) end of transfer 53 m pd17145(a1), 17147(a1), 17149(a1) (2) 8-bit reception mode (so pin: high-impedance state) the p0d 1 /so pin goes into a high-impedance state when siohiz = 1. if supply of the serial clock is started at this time by writing 1 to siots, the serial interface only receives data. because the p0d 1 /so pin goes into a high-impedance state, it can be used as an input port pin (p0d 1 ). figure 15-3. timing in 8-bit reception mode remark di: serial data input (3) operation stop mode when the value of siots (rf: address 02h, bit 3) is 0, the serial interface is set in the operation stop mode. in this mode, serial transfer is not executed. because the shift register does not perform the shift operation in this mode, it can be used as an ordinary 8-bit register. 12345678 di7 di6 di5 di4 di3 di2 di1 di0 sck pin si pin so pin irqsio hi - z starts transfer in synchronization with falling of sck pin executes instruction that writes "1" to siots ( transfer start command ) end of transfer 54 m pd17145(a1), 17147(a1), 17149(a1) 16. interrupt function the m pd17149(a1) has five interrupt causes, of which four are internal and one is external, enabling various applications. the interrupt control circuit of the m pd17149(a1) has the following features and can perform interrupt processing at extremely high speeds: (a) acknowledging an interrupt can be controlled by interrupt mask enable flag (inte) and interrupt enable flag (ip ). (b) interrupt request flags (irq ) can be tested and cleared (occurrence of an interrupt can be checked by software). (c) multiple interrupts of up to 3 levels can be processed. (d) the standby mode (stop or halt) can be released by an interrupt request (releasing condition can be selected by the interrupt enable flag). caution only the bcd, cmp, cy, z, and ixe flags are automatically saved to the stack by hardware when interrupt processing is performed. up to three levels of multiple interrupts can be processed. if the peripheral hardware (timers, a/d converter, etc.) is accessed during interrupt processing, the contents of dbf and wr are not saved by the hardware. it is therefore recommended that dbf and wr be saved to the ram by software at the beginning of interrupt processing, and that their contents be restored immediately before the interrupt processing. 16.1 types of interrupt causes and vector addresses all the interrupts of the m pd17149 (a1) are vectored interrupts, and therefore, program execution branches to a vector address corresponding to the interrupt cause when an interrupt has been acknowledged. table 16- 1 shows the types of interrupt causes and vector addresses. if two or more interrupts occur at the same time, or if two or more pending interrupts are enabled all at once, processing is performed according to the priority shown in table 16-1. table 16-1. types of interrupt causes vector internal interrupt cause priority irq flag ip flag ieg flag remark address /external int pin 1 0005h irq ip iegmd0, 1 external rising, falling, or (rf: 0fh, bit 0) rf: 3fh, rf: 2fh, rf:1fh both rising and fall- bit 0 bit 0 ing edges selectable timer 0 2 0004h irqtm0 iptm0 internal rf: 3eh, rf: 2fh, ? bit 0 bit 1 timer 1 3 0003h irqtm1 iptm1 internal rf: 3dh, rf: 2fh, ? bit 0 bit 2 basic interval 4 0002h irqbtm ipbtm ? internal timer rf: 3ch, rf: 2fh, bit 0 bit 3 serial interface 5 0001h irqsio ipsio internal rf: 3bh, rf: 2eh, ? bit 0 bit 0 55 m pd17145(a1), 17147(a1), 17149(a1) 16.2 hardware of interrupt control circuit this section describes each flag of the interrupt control circuit. (1) interrupt request flags and interrupt enable flags an interrupt request flag (irq ) is set to 1 when an interrupt request is generated, and automatically cleared to 0 when interrupt processing is executed. an interrupt enable flag (ip ) is provided for each interrupt request flag. the corresponding interrupt is enabled when this flag is 1, and disabled when the flag is 0. (2) ei/di instruction whether an interrupt that has been acknowledged is executed is specified by the ei or di instruction. when the ei instruction is executed, an interrupt enable flag (inte) that enables acknowledging an interrupt is set to 1. the inte flag is not registered on the register file. therefore, the status of this flag cannot be checked by an instruction. the di instruction clears the inte flag to 0, disabling all the interrupts. the inte flag is also cleared to 0 at reset, and therefore all the interrupts are disabled. table 16-2. interrupt request flags and interrupt enable flags interrupt request flag interrupt request flag setting signal interrupt enable flag irq sets when edge of int pin input signal is detected. ip edge to be detected is selected by iegmd0 and iegmd1 flags. irqtm0 set by coincidence signal from timer 0. iptm0 irqtm1 set by coincidence signal from timer 1. iptm1 irqbtm set by overflow from basic interval timer (reference time ipbtm interval signal). irqsio set when serial interface completes serial data transfer. ipsio 56 m pd17145(a1), 17147(a1), 17149(a1) 17. standby function 17.1 outline of standby function the current dissipation of the m pd17149(a1) can be reduced by using the standby function. this function can be effected in two modes: stop and halt. the stop mode stops the system clock. in this mode, the current dissipation by the cpu is minimized with only leakage current flowing. the cpu therefore does not operate, but the contents of the data memory are retained. in the halt mode, oscillation of the clock continues. however, supply of the clock to the cpu is stopped. therefore, the cpu stops operating. this mode cannot reduce the current dissipation as much as the stop mode. however, because the system clock continues oscillating, the operation can be started immediately after the halt mode has been released. in both the stop and halt modes, the statuses of the data memory, registers, and the output latches of the output ports immediately before the standby mode is set are retained (except stop 0000b). therefore, set the port status so that the current dissipation of the entire system is reduced before the standby mode is set. 57 m pd17145(a1), 17147(a1), 17149(a1) table 17-1. status in standby mode stop mode halt mode setting stop instruction halt instruction instruction clock oscillation stops oscillation continues oscillation circuit cpu stops operation ram retains previous status port retains previous status note tm0 can operate only when int input is selected operable as count clock stops when system clock is selected (count value is retained) tm1 stops operation operable (count value is reset to 0) (count up is disabled) btm stops operation (count value is retained) operable sio can operate only when external clock is operable selected as serial clock note a/d stops operation note (adcr <- 00h) operable int can operate operable note as soon as the stop 0000b instruction is executed, the pins of these peripherals are set in the input port mode, even when the control signal functions of the pins are used. cautions 1. be sure to execute the nop instruction immediately before the stop and halt instructions. 2. if both the interrupt request flag and interrupt enable flag corresponding to an interrupt are set, and if the interrupt is specified to release the standby mode, the standby mode is not set even if the stop or halt instruction is executed. operating status 58 m pd17145(a1), 17147(a1), 17149(a1) 17.2 halt mode 17.2.1 setting halt mode the halt mode is set when the halt instruction is executed. the operand of the halt instruction, b 3 b 2 b 1 b 0 , specifies the condition under which the halt mode is released. table 17-2. halt mode releasing condition format: halt b 3 b 2 b 1 b 0 b bit halt mode releasing condition note 1 b 3 enables releasing halt mode by irq when 1 notes 2, 4 b 2 fixed to 0 b 1 enables forced release of halt mode by irqtm1 when 1 notes 3, 4 b 0 enables releasing halt mode by rls input when 1 note 4 notes 1. only reset (reset input or poc) is valid when halt 0000b is specified. 2. ip must be set to 1. 3. the halt mode is released regardless of the status of iptm1. 4. even if the halt instruction is executed with irq = 1 or rls input being low, the halt instruction is ignored (treated as an nop instruction), and the halt mode is not set. 17.2.2 start address after halt mode is released the start address from which the program execution is started after the halt mode has been released differs depending on the interrupt enable condition and the condition under which the halt mode has been released. table 17-3. start address after halt mode is released releasing condition start address after release reset note 1 address 0 rls address next to that of halt instruction address next to that of halt instruction in di status irq note 2 interrupt vector in ei status (if two or more irq flags are set, interrupt vector with higher priority) notes 1. reset input and poc are valid as reset. 2. ip must be set to 1 except when the halt mode is forcibly released by irqtm1. 59 m pd17145(a1), 17147(a1), 17149(a1) figure 17-1. releasing halt mode (a) by reset input (b) by rls input (c) by irq (in di status) (d) by irq (in ei status) interrupt processing acknowledged irq halt instruction executed operation mode halt mode operation mode halt instruction executed tm1 counts up operation mode halt mode system reset status wait a operation mode (starts from address 0) wait a : wait time until tm1 counts 256 clocks divided by 128 256 128/f x (approx. 4 ms at f x =8 mhz) reset halt instruction executed operation mode halt mode operation mode rls irq halt instruction executed operation mode halt mode operation mode 60 m pd17145(a1), 17147(a1), 17149(a1) 17.3 stop mode 17.3.1 setting stop mode the stop mode is set when the stop instruction is executed. the operand of the stop instruction, b 3 b 2 b 1 b 0 , specifies the condition under which the stop mode is released. table 17-4. stop mode releasing condition format: stop b 3 b 2 b 1 b 0 b bit stop mode releasing condition note 1 b 3 enables releasing halt mode by irq when 1 notes 2, 4 b 2 fixed to 0 b 1 fixed to 0 b 0 enables releasing stop mode by rls input when 1 notes 3, 4 notes 1. only reset (reset input or poc) is valid when stop 0000b is specified. when stop 0000b is executed, the internal circuitry of the microcontroller is initialized to the status immediately after reset. 2. ip must be set to 1. the stop mode cannot be released by irqtm1. 3. b 0 alone cannot be set to 1 (stop 0001b is prohibited). before setting b 0 to 1, be sure to set b 3 to 1. 4. even if the stop instruction is executed with irq = 1 or the rls input being low, the stop instruction is ignored (treated as an nop instruction), and the stop mode is not set. 17.3.2 start address after stop mode is released the start address from which the program execution is started after the stop mode has been released differs depending on the condition under which the stop mode has been released, and interrupt enable condition. table 17-5. start address after stop mode is released releasing condition start address after release reset note 1 address 0 rls address next to that of stop instruction address next to that of halt instruction in di status irq note 2 interrupt vector in ei status (if two or more irq flags are set, interrupt vector with higher priority) notes 1. reset input and poc are valid as reset. 2. ip must be set to 1. the stop mode cannot be released by irqtm1. 61 m pd17145(a1), 17147(a1), 17149(a1) figure 17-2. releasing stop mode (a) by reset input (b) by rls input (c) by irq (in di status) reset stop instruction executed tm1 counts up operation mode stop mode system reset status wait b operation mode (starts from address 0) wait b : wait time until tm1 counts 256 clocks divided by 128 256 128/f x + (apporox. 4 ms + at f x = 8 mhz) : oscillation growth time (differs depending on the oscillator) a aa rls stop instruction executed tm1 counts up operation mode stop mode wait c operation mode wait c : wait time until tm1 counts clocks divided by m n times n m/f x + (n and m are values immediately before stop mode is set) : oscillation growth time (differs depending on the oscillator) a a irq tm1 counts up operation mode stop mode wait c operation mode wait c : wait time until tm1 counts clocks divided by m n times n m/f x + (n and m are values immediately before stop mode is set) : oscillation g rowth time ( differs dependin g on the oscillator ) stop instruction executed a a 62 m pd17145(a1), 17147(a1), 17149(a1) (d) by irq (in ei status) irq stop instruction executed tm1 counts up, interrupt processing acknowledged operation mode stop mode wait c operation mode wait c : wait time until tm1 counts clocks divided by m n times n m/f x + (n and m are values immediately before stop mode is set) : oscillation growth time (differs depending on the oscillator) a a 63 m pd17145(a1), 17147(a1), 17149(a1) 18. reset the m pd17149 (a1) can be reset not only by the reset input, but also by the internal poc circuit that detects a supply voltage drop, watchdog timer function that resets the microcontroller if program runaway occurs, and overflow or underflow of the address stack. note, however, that the internal poc circuit is a mask option. 18.1 reset function the reset function initializes the device operation. how the device is initialized differs depending on the type of reset. table 18-1. hardware status at reset overflow of watchdog timer overflow and underflow of stack reset input in standby mode reset by internal poc circuit in standby mode reset input during operation reset by internal poc circuit program counter 0000h 0000h 0000h input/output input input input contents of output latch general-purpose data memory undefined retains contents undefined (except dbf) dbf undefined undefined undefined system register (except wr) wr undefined retains contents undefined control register timer 0: 00h, timer 1: undefined modulo register ffh ffh ffh binary counter of basic interval timer undefined undefined shift register (siosfr) undefined retains contents undefined output latch 0 0 undefined data register of a/d converter (adcr) 00h 00h 00h type of reset port 0 0 undefined 00 0 count register 00h 00h timer 0 and timer 1 sp = 5h, irqtm1 = 1, tm1en = 1, irqbtm = 1, int = status at that time. others are 0. refer to 8. register file (rf). sp = 5h, int = status at that time. others retain contents. undefined. however, 40h if watchdog timer overflows. serial interface general-purpose data memory hardware 64 m pd17145(a1), 17147(a1), 17149(a1) figure 18-1. configuration of reset block 18.2 reset operation figure 18-2 shows the operation when the system is reset by using the reset pin. when the reset pin is made high, oscillation of the system clock is started, oscillation stabilization wait time specified by timer 1 elapses, and program execution is started from address 0000h. these operations are also performed if the system is reset by the poc circuit. if the system is reset by using an overflow of the watchdog timer or an overflow or underflow of the stack, the oscillation stabilization wait time (wait a) does not elapse, and program execution is started from address 0000h after the internal circuitry has been initialized. figure 18-2. reset operation note oscillation stabilization wait time. an operation mode is set when system clock is counted 128 256 times by timer 1 (time required to executed 2048 instructions: approx. 4 ms at 8 mhz). mask option reset v dd internal reset signal poc circuit (mask option) reset tm1en tm1res operation mode reset wait a note operation mode 65 m pd17145(a1), 17147(a1), 17149(a1) 19. poc circuit (mask option) the poc circuit monitors the supply voltage. when the supply voltage is turned on/off, it automatically resets the internal circuitry of the microcontroller. this circuit can be used in an application circuit with a clock frequency of 400 khz to 4 mhz. the m pd17149 (a1) can be provided with the poc circuit by mask option. caution the poc circuit is not provided to the prom model ( m pd17p149). 19.1 function of poc circuit the poc circuit has the following functions: generates internal reset signal when v dd v poc clears internal reset signal when v dd > v poc (where, v dd : supply voltage, v poc : poc detection voltage) figure 19-1. operation of poc circuit 5.5 v 4.5 v v poc 2.7 v 0 v note 3 v dd note 1 ? t reset operation mode note 4 reset operation guaranteed range internal reset signal - note 2 note 3 66 m pd17145(a1), 17147(a1), 17149(a1) notes 1. actually, oscillation stabilization wait time specified by timer 1 elapses before the operation mode is set. this time is equal to that required for executing about 2048 instructions (approx. 8 ms at 4 mhz). 2. to reset the microcontroller again when the supply voltage drops, the status in which the voltage drops below v poc must be maintained at least for the duration of the reset detection pulse width t samp . therefore, reset is actually effected with a delay time of up to t samp . 3. the operation is not guaranteed if the supply voltage drops below the rated minimum value (2.7 v). however, the poc circuit is designed to generate the internal reset signal so long as it is possible, regardless of oscillation. therefore, the internal circuitry is reset when the voltage supplied to it has reached the level at which the circuitry can operate. 4. if the supply voltage abruptly increases (3 v/ms min.), the poc circuit may generate the internal reset signal, even in an operation mode, to prevent program runaway. remark for the values of v poc and t samp , refer to 22. electrical specifications . 19.2 conditions to use poc circuit the poc circuit can be used when the application circuit satisfies the following conditions: the application circuit does not require a high reliability. the operating voltage must range from 4.5 to 5.5 v. the clock frequency must range from 400 khz to 4 mhz. the supply voltage must satisfy the ratings of the poc circuit. cautions 1. if the application circuit requires an extremely high reliability, design the circuit so that the reset signal is input from an external source. 2. the current dissipation in the standby mode slightly increases if the poc circuit is used. remark the guaranteed operating voltage range of the poc circuit is v dd = 2.7 to 5.5 v. 67 m pd17145(a1), 17147(a1), 17149(a1) 20. instruction set 20.1 outline of instruction set b 15 b 14 -b 11 01 bin hex 0000 0 add r, m add m, #n4 0001 1 sub r, m sub m, #n4 0010 2 addc r, m addc m, #n4 0011 3 subc r, m subc m, #n4 0100 4 and r, m and m, #n4 0101 5 xor r, m xor m, #n4 0110 6 or r, m or m, #n4 inc ar inc ix movt dbf, @ar br @ar call @ar ret retsk ei di 0111 7 reti push ar pop ar get dbf, p put p, dbf peek wr, rf poke rf, wr rorc r stop s halt h nop 1000 8 ld r, m st m, r 1001 9 ske m, #n4 skge m, #n4 1010 a mov @r, m mov m, @r 1011 b skne m, #n4 sklt m, #n4 1100 c br addr (page 0) call addr 1101 d br addr (page 1) mov m, #n4 1110 e skt m, #n 1111 f skf m, #n 68 m pd17145(a1), 17147(a1), 17149(a1) 20.2 legend ar : address register asr : address stack register indicated by stack pointer addr : program memory address (lower 11 bits) bank : bank register cmp : compare flag cy : carry flag dbf : data buffer h : halt release condition intef : interrupt enable flag intr : register automatically saved to the stack when interrupt processing is performed intsk : interrupt stack register ix : index register mp : data memory row address pointer mpe : memory pointer enable flag m : data memory address indicated by m r , m c m r : data memory row address (high) m c : data memory column address (low) n : bit position (4 bits) n4 : immediate data (4 bits) page : page (bit 11 of program counter) pc : program counter p : peripheral address p h : peripheral address (higher 3 bits) p l : peripheral address (lower 4 bits) r : general register column address rf : register file address rf r : register file row address (higher 3 bits) rf c : register file column address (lower 4 bits) sp : stack pointer s : stop release condition wr : window register ( ) : contents addressed by 69 m pd17145(a1), 17147(a1), 17149(a1) in- struc- tion m, @r 11010 m r m c r @r, m 01010 m r m c r rorc r 00111 000 0111 r addition subtraction logical operation judgment comparison rotation transfer add addc inc sub subc or and xor movt dvf, @ar 00111 000 0001 0000 20.3 instruction set instruction code mnemonic operand operation op code operand r, m (r) ? (r) + (m) 00000 m r m c r m, #n4 (m) ? (m) + n4 10000 m r m c n4 r, m (r) ? (r) + (m) + cy 00010 m r m c r m, #n4 (m) ? (m) + n4 + cy 10010 m r m c n4 ar ar ? ar + 1 00111 000 1001 0000 ix ix ? ix + 1 00111 000 1000 0000 r, m (r) ? (r) e (m) 00001 m r m c r m, #n4 (m) ? (m) e n4 10001 m r m c n4 r, m (r) ? (r) e (m) e cy 00011 m r m c r m, #n4 (m) ? (m) e n4 e cy 10011 m r m c n4 r, m (r) ? (r) (m) 00110 m r m c r m, #n4 (m) ? (m) n4 10110 m r m c n4 r, m (r) ? (r) (m) 00100 m r m c r m, #n4 (m) ? (m) n4 10100 m r m c n4 r, m (r) ? (r) (m) 00101 m r m c r m, #n4 (m) ? (m) n4 10101 m r m c n4 skt m, #n cmp ? 0, if (m) n = n, then skip 11110 m r m c n skf m, #n cmp ? 0, if (m) n = 0, then skip 11111 m r m c n ske m, #n4 (m) e n4, skip if zero 01001 m r m c n4 skne m, #n4 (m) e n4, skip if not zero 01011 m r m c n4 skge m, #n4 (m) e n4, skip if not borrow 11001 m r m c n4 sklt m, #n4 (m) e n4, skip if borrow 11011 m r m c n4 ? cy ? (r) b 3 ? (r) b 2 ? (r) b 1 ? (r) b 0 ld r, m (r) ? (m) 01000 m r m c r st m, r (m) ? (r) 11000 m r m c r if mpe = 1: (mp, (r)) ? (m) if mpe = 0: (bank, m r , (r)) ? (m) mov if mpe = 1: (m) ? (mp, (r)) if mpe = 0: (m) ? (bank, m r , (r)) m, #n4 (m) ? n4 11101 m r m c n4 sp ? sp e1, asr ? pc, pc ? ar, dbf ? (pc), pc ? asr, sp ? sp +1 push ar sp ? sp e1, asr ? ar 00111 000 1101 0000 pop ar ar ? asr, sp ? sp +1 00111 000 1100 0000 peek wr, rf wr ? (rf) 00111 rf r 0011 rf c poke rf, wr (rf) ? wr 00111 rf r 0010 rf c get dbf, p dbf ? (p) 00111 p h 1011 p l put p, dbf (p) ? dbf 00111 p h 1010 p l 70 m pd17145(a1), 17147(a1), 17149(a1) br addr instruction code mnemonic operand operation op code operand addr note note addr @ar pc ? ar 00111 000 0100 0000 sp ? sp e 1, asr ? pc, pc ? addr sp ? sp e 1, asr ? pc, pc ? ar ret pc ? asr, sp ? sp + 1 00111 000 1110 0000 retsk pc ? asr, sp ? sp + 1 and skip 00111 001 1110 0000 reti pc ? asr, intr ? intsk, sp ? sp + 1 00111 100 1110 0000 ei intef ? 1 00111 000 1111 0000 di intef ? 0 00111 001 1111 0000 stop s stop 00111 010 1111 s halt h halt 00111 011 1111 h nop no operation 00111 100 1111 0000 note the operation and op code of br addr of the m pd17145(a1), 17147(a1), and m pd17149(a1) are as follows: (a) m pd17145(a1), 17147(a1) mnemonic operand operation op code br addr pc ? addr, page ? 0 01100 (b) m pd17149(a1) mnemonic operand operation op code pc ? addr, page ? 0 01100 pc ? addr, page ? 1 01101 in- struc- tion br call @ar 00111 000 0101 0000 addr 11100 addr branch subroutine interrupt others 71 m pd17145(a1), 17147(a1), 17149(a1) 20.4 assembler (as17k) embedded macro instruction legend flag n: flg type symbol < >: can be omitted mnemonic operand operation n sktn flag 1, flag n if (flag 1) to (flag n) = all 1, then skip 1 n 4 skfn flag 1, flag n if (flag 1) to (flag n) = all0, then skip 1 n 4 setn flag 1, flag n (flag 1) to (flag n) ? 11 n 4 clrn flag 1, flag n (flag 1) to (flag n) ? 01 n 4 if (flag n) = 0, then (flag n) ? 1 if (flag n) = 1, then (flag n) ? 0 72 m pd17145(a1), 17147(a1), 17149(a1) 21. assembler reserved words 21.1 mask option directive the m pd17149 (a1) has the following mask options: internal pull-up resistor of reset pin internal pull-up resistor of p0f 1 and p0f 0 pins internal pull-up resistor of int pin internal poc circuit when developing a program, it is necessary to specify all the above mask options in the source program by using a mask option definition directive (pseudo instruction). 21.1.1 specifying mask option the mask option is described in the assembler source program by using the following directives: option directive, endop directive mask option definition directive (1) option and endop directives these directives specify the range in which the mask option is specified (mask option definition block). specify the mask option by describing a mask option definition directive in the area sandwiched between the option and endop directives. format symbol field mnemonic field operand field comment field [label:] option [;comment] endop 73 m pd17145(a1), 17147(a1), 17149(a1) (2) mask option definition directives table 21-1. mask option definition directives option definition directive and format operand defined contents internal pull-up resistor optres 74 m pd17145(a1), 17147(a1), 17149(a1) 21.2 reserved symbols the following tables show the reserved symbols defined by the device file (as17149) of the m pd17149(a1): system register (sysreg) symbol name attribute value read/write description ar3 mem 0.74h r bits b15-b12 of address register ar2 mem 0.75h r/w bits b11-b8 of address register ar1 mem 0.76h r/w bits b7-b4 of address register ar0 mem 0.77h r/w bits b3-b0 of address register wr mem 0.78h r/w window register bank mem 0.79h r/w bank register ixh mem 0.7ah r/w index register, high mph mem 0.7ah r/w data memory row address pointer, high mpe flg 0.7ah.3 r/w memory pointer enable flag ixm mem 0.7bh r/w index register, middle mpl mem 0.7bh r/w data memory row address pointer, low ixl mem 0.7ch r/w index register, low rph mem 0.7dh r/w general register pointer, high rpl mem 0.7eh r/w general register pointer, low psw mem 0.7fh r/w program status word bcd flg 0.7eh.0 r/w bcd flag cmp flg 0.7fh.3 r/w compare flag cy flg 0.7fh.2 r/w carry flag z flg 0.7fh.1 r/w zero flag ixe flg 0.7fh.0 r/w index enable flag 75 m pd17145(a1), 17147(a1), 17149(a1) figure 21-1. configuration of system register notes 1. 0 in this field means that the bit is fixed to 0. 2. b 3 and b 2 of ar2 of the m pd17145 (a1) are fixed to 0. b 3 of ar2 of the m pd17147 (a1) is fixed to 0. address name symbol bit data note 1 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh ar3 ar2 ar1 ar0 wr bank ixh ixm ixl rph rpl psw mph mpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0000000000000000 0000000000000000000000000000 0000 0000 0000 0000 (rp) (mp) (ix) (bank) (ar) m p e b c d c m p c yz i x e address register (ar) bank register (bank) index register (ix) data memory row address pointer (mp) undefined note 2 initial value at reset window register (wr) general register pointer (rp) program status word (psword) 76 m pd17145(a1), 17147(a1), 17149(a1) data buffer (dbf) symbol name attribute value read/write description dbf3 mem 0.0ch r/w bits 15 to 12 of dbf dbf2 mem 0.0dh r/w bits 11 to 8 of dbf dbf1 mem 0.0eh r/w bits 7 to 4 of dbf dbf0 mem 0.0fh r/w bits 3 to 0 of dbf port register symbol name attribute value read/write description p0a3 flg 0.70h.3 r/w bit 3 of port 0a p0a2 flg 0.70h.2 r/w bit 2 of port 0a p0a1 flg 0.70h.1 r/w bit 1 of port 0a p0a0 flg 0.70h.0 r/w bit 0 of port 0a p0b3 flg 0.71h.3 r/w bit 3 of port 0b p0b2 flg 0.71h.2 r/w bit 2 of port 0b p0b1 flg 0.71h.1 r/w bit 1 of port 0b p0b0 flg 0.71h.0 r/w bit 0 of port 0b p0c3 flg 0.72h.3 r/w bit 3 of port 0c p0c2 flg 0.72h.2 r/w bit 2 of port 0c p0c1 flg 0.72h.1 r/w bit 1 of port 0c p0c0 flg 0.72h.0 r/w bit 0 of port 0c p0d3 flg 0.73h.3 r/w bit 3 of port 0d p0d2 flg 0.73h.2 r/w bit 2 of port 0d p0d1 flg 0.73h.1 r/w bit 1 of port 0d p0d0 flg 0.73h.0 r/w bit 0 of port 0d p0e3 flg 0.6eh.3 r/w bit 3 of port 0e p0e2 flg 0.6eh.2 r/w bit 2 of port 0e p0e1 flg 0.6eh.1 r/w bit 1 of port 0e p0e0 flg 0.6eh.0 r/w bit 0 of port 0e p0f1 flg 0.6fh.1 r bit 1 of port 0f p0f0 flg 0.6fh.0 r bit 0 of port 0f 77 m pd17145(a1), 17147(a1), 17149(a1) register file (control registers) symbol name attribute value read/write description sp mem 0.81h r/w stack pointer siots flg 0.82h.3 r/w serial interface start flag siohiz flg 0.82h.2 r/w p0d 1 /so pin function select flag siock1 flg 0.82h.1 r/w bit 1 of serial clock select flag siock0 flg 0.82h.0 r/w bit 0 of serial clock select flag wdtres flg 0.83h.3 r/w watchdog timer reset flag wdten flg 0.83h.0 r/w watchdog timer enable flag tm1osel flg 0.8bh.3 r/w p0d 3 /tm1out pin function select flag sioen flg 0.8bh.0 r/w serial interface enable flag p0egpu flg 0.8ch.2 r/w p0e group pull-up select flag (pull-up = 1) p0bgpu flg 0.8ch.1 r/w p0b group pull-up select flag (pull-up = 1) p0agpu flg 0.8ch.0 r/w p0a group pull-up select flag (pull-up = 1) p0dbpu3 flg 0.8dh.3 r/w p0d 3 pull-up select flag (pull-up = 1) p0dbpu2 flg 0.8dh.2 r/w p0d 2 pull-up select flag (pull-up = 1) p0dbpu1 flg 0.8dh.1 r/w p0d 1 pull-up select flag (pull-up = 1) p0dbpu0 flg 0.8dh.0 r/w p0d 0 pull-up select flag (pull-up = 1) int flg 0.8fh.0 r int pin status flag tm0en flg 0.91h.3 r/w timer 0 enable flag tm0res flg 0.91h.2 r/w timer 0 reset flag tm0ck1 flg 0.91h.1 r/w bit 1 of timer 0 count pulse select flag tm0ck0 flg 0.91h.0 r/w bit 0 of timer 0 count pulse select flag tm1en flg 0.92h.3 r/w timer 1 enable flag tm1res flg 0.92h.2 r/w timer 1 reset flag tm1ck1 flg 0.92h.1 r/w bit 1 of timer 1 count pulse select flag tm1ck0 flg 0.92h.0 r/w bit 0 of timer 1 count pulse select flag btmisel flg 0.93h.3 r/w basic interval timer interrupt request clock select flag btmres flg 0.93h.2 r/w basic interval timer reset flag btmck1 flg 0.93h.1 r/w bit 1 of basic interval timer count pulse select flag btmck0 flg 0.93h.0 r/w bit 0 of basic interval timer count pulse select flag p0c3idi flg 0.9bh.3 r/w p0c 3 input port disable flag (selects adc 3 /p0c 3 pin function) p0c2idi flg 0.9bh.2 r/w p0c 2 input port disable flag (selects adc 2 /p0c 2 pin function) p0c1idi flg 0.9bh.1 r/w p0c 1 input port disable flag (selects adc 1 /p0c 1 pin function) p0c0idi flg 0.9bh.0 r/w p0c 0 input port disable flag (selects adc 0 /p0c 0 pin function) p0cbio3 flg 0.9ch.3 r/w p0c 3 input/output select flag (1 = output port) p0cbio2 flg 0.9ch.2 r/w p0c 2 input/output select flag (1 = output port) p0cbio1 flg 0.9ch.1 r/w p0c 1 input/output select flag (1 = output port) p0cbio0 flg 0.9ch.0 r/w p0c 0 input/output select flag (1 = output port) iegmd1 flg 0.9fh.1 r/w bit 1 of int pin edge detection select flag iegmd0 flg 0.9fh.0 r/w bit 0 of int pin edge detection select flag 78 m pd17145(a1), 17147(a1), 17149(a1) register file (control registers) symbol name attribute value read/write description adcstrt flg 0.0a0h.0 r/w a/d converter start flag (read: always 0) adcsoft flg 0.0a1h.3 r/w a/d converter mode select flag (1 = single mode) adccmp flg 0.0a1h.1 r a/d converter comparator comparison result flag (valid only in single mode) adcend flg 0.0a1h.0 r a/d converter conversion end flag adcch3 flg 0.0a2h.3 r/w dummy flag adcch2 flg 0.0a2h.2 r/w dummy flag adcch1 flg 0.0a2h.1 r/w bit 1 of a/d converter channel select flag adcch0 flg 0.0a2h.0 r/w bit 0 of a/d converter channel select flag p0dbio3 flg 0.0abh.3 r/w p0d 3 input/output select flag (1 = output port) p0dbio2 flg 0.0abh.2 r/w p0d 2 input/output select flag (1 = output port) p0dbio1 flg 0.0abh.1 r/w p0d 1 input/output select flag (1 = output port) p0dbio0 flg 0.0abh.0 r/w p0d 0 input/output select flag (1 = output port) p0egio flg 0.0ach.2 r/w p0e group input/output select flag (1 = all p0e as output port) p0bgio flg 0.0ach.1 r/w p0b group input/output select flag (1 = all p0b as output port) p0agio flg 0.0ach.0 r/w p0a group input/output select flag (1 = all p0a as output port) ipsio flg 0.0aeh.0 r/w serial interface interrupt enable flag ipbtm flg 0.0afh.3 r/w basic interval timer interrupt enable flag iptm1 flg 0.0afh.2 r/w timer 1 interrupt enable flag iptm0 flg 0.0afh.1 r/w timer 0 interrupt enable flag ip flg 0.0afh.0 r/w int pin interrupt enable flag irqsio flg 0.0bbh.0 r/w serial interface interrupt request flag irqbtm flg 0.0bch.0 r/w basic interval timer interrupt request flag irqtm1 flg 0.0bdh.0 r/w timer 1 interrupt request flag irqtm0 flg 0.0beh.0 r/w timer 0 interrupt request flag irq flg 0.0bfh.0 r/w int pin interrupt request flag 79 m pd17145(a1), 17147(a1), 17149(a1) peripheral hardware registers symbol name attribute value read/write description siosfr dat 01h r/w peripheral address of shift register tm0m dat 02h w peripheral address of timer 0 modulo register tm1m dat 03h w peripheral address of timer 1 modulo register adcr dat 04h r/w peripheral address of a/d converter data register tm0tm1c dat 45h r peripheral address of timer 0 timer 1 count register ar dat 40h r/w peripheral address of address register for get/put/ push/call/br/movt/inc instruction others symbol name attribute value description dbf dat 0fh fixed operand value of put, get, and movt instructions ix dat 01h fixed operand value of inc instruction 80 m pd17145(a1), 17147(a1), 17149(a1) figure 21-2. configuration of control register remark ( ) is the address when the assembler (as17k) is used. all the flags of the control register are registered to the device file as assembler reserved words, and are convenient for program development. column address row address item 0 (8) 1 (9) 2 (a) 3 (b) 01 234 567 symbol s i o t s s i o h i z s i o c k 1 s i o c k 0 w d t r e s 00 w d t e n 0 s p 010100000000 r/w r/w r/w read/ write at reset symbol symbol at reset read/ write at reset read/ write symbol at reset read/ write r/w r/w r/w r/w r/w r/w t m 0 e n t m 0 r e s t m 0 c k 1 t m 0 c k 0 t m 1 e n t m 1 r e s t m 1 c k 1 t m 1 c k 0 b t m i s e l b t m r e s b t m c k 1 b t m c k 0 000 a d c s t r t a d c s o f t 0 a d c c m p a d c e n d a d c c h 3 a d c c h 2 a d c c h 1 a d c c h 0 000010000000 000000000000 r 81 m pd17145(a1), 17147(a1), 17149(a1) figure 21-2. configuration of control register note int flag differs depending on the status of the int pin at that time. f ce d b a 9 8 note 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 0 01 0 0 00 0 0 00 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w i n t 0 0 0 p 0 d b p u 0 p 0 d b p u 1 p 0 d b p u 2 p 0 d b p u 3 p 0 a g p u p 0 b g p u p 0 e g p u 0 s i o e n 0 0 t m 1 o s e l p 0 c 0 i d i p 0 c 1 i d i p 0 c 2 i d i p 0 c 3 i d i p 0 c b i o 0 p 0 c b i o 1 p 0 c b i o 2 p 0 c b i o 3 i e g m d 0 i e g m d 1 0 0 i p i p t m 0 i p t m 1 i p b t m i p s i o 0 0 0 p 0 a g i o p 0 b g i o p 0 e g i o 0 p 0 d b i o 0 p 0 d b i o 1 p 0 d b i o 2 p 0 d b i o 3 i r q s i o 0 0 0 i r q b t m 0 0 0 i r q t m 1 0 0 0 i r q t m 0 0 0 0 i r q 0 0 0 82 m pd17145(a1), 17147(a1), 17149(a1) 22. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol condition ratings unit supply voltage v dd e0.3 to +7.0 v a/d converter reference voltage v ref e0.3 to v dd + 0.3 v p0a, p0b, p0c, p0d, p0e, p0f, int, reset, x in output voltage v o e0.3 to v dd + 0.3 v per p0a, p0b, or p0c peak value e15 ma effective value e7.5 ma total of p0a, p0b, peak value e30 ma and p0c effective value e15 ma per p0a, p0b, or p0c peak value 15 ma effective value 7.5 ma per p0d or p0e peak value 30 ma effective value 15 ma total of p0a, p0b, p0c, peak value 100 ma p0d, and p0e effective value 50 ma operating temperature t opt e40 to +110 c storage temperature t stg e65 to +150 c 28-pin plastic shrink dip 140 mw 28-pin plastic sop 85 mw note [effective value] = [peak value] ? duty caution if the value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings are the values exceeding which may physically damage the product. be sure to use the product with these values not exceeded. recommended supply voltage range (t a = e40 to +110 c) parameter symbol condition min. typ. max. unit f x = 400 khz to 2 mhz 2.7 5.5 v f x = 400 khz to 4 mhz 3.6 5.5 v f x = 400 khz to 8 mhz 4.5 5.5 v supply voltage v dd a/d converter 4.0 5.5 v poc circuit (mask option) f x = 400 khz to 4 mhz 4.5 5.5 v absolute accuracy: 1.5lsb, 2.5 v v ref v dd input voltage v i e0.3 to v dd + 0.3 v high-level output current i oh note low-level output current i ol note power dissipation p d t a = 85 c cpu (other than a/d converter and poc circuit) 83 m pd17145(a1), 17147(a1), 17149(a1) output voltage, low output voltage, high v oh p0a, p0b, p0c dc characteristics (v dd = 2.7 to 5.5 v, t a = e40 to +110 c) parameter symbol condition min. typ. max. unit v ih1 p0a, p0b, p0c, p0d, p0e, p0f 0.7v dd v dd v input voltage, high v ih2 reset, sck, si, int 0.8v dd v dd v v ih3 x in v dd e 0.5 v dd v v il1 p0a, p0b, p0c, p0d, p0e, p0f 0 0.3v dd v input voltage, low v il2 reset, sck, si, int 0 0.2v dd v v il3 x in 0 0.4 v 4.5 v dd 5.5 v dd e 0.3 v i oh = e1.0 ma 2.7 v dd < 4.5 v dd e 0.3 v i oh = e0.5 ma 4.5 v dd 5.5 0.3 v i ol = 1.0 ma 2.7 v dd < 4.5 0.3 v i ol = 0.5 ma p0d, p0e 4.5 v dd 5.5 1.0 v v ol2 i ol = 15 ma 2.7 v dd < 4.5 2.0 v input leakage current, high i lih p0a, p0b, p0c, p0d, p0e, p0f v in = v dd 5 m a input leakage current, low i lil p0a, p0b, p0c, p0d, p0e, p0f v in = 0 v e5 m a output leakage current, high i loh p0a, p0b, p0c, p0d, p0e v out = v dd 5 m a output leakage current, low i lol p0a, p0b, p0c, p0d, p0e v out = 0 v e5 m a p0a, p0b, p0e, p0f, reset, int 50 100 250 k w p0d 3 10 30 k w f x = 8.0 mhz v dd = 5 v 10 % 2.0 4.5 ma f x = 4.0 mhz v dd = 5 v 10 % 1.4 3.3 ma i dd1 operation mode f x = 2.0 mhz v dd = 3 v 10 % 0.5 1.5 ma f x = 400 khz v dd = 5 v 10 % 0.9 1.7 ma v dd = 3 v 10 % 0.3 1.0 ma f x = 8.0 mhz v dd = 5 v 10 % 1.0 2.0 ma f x = 4.0 mhz v dd = 5 v 10 % 0.9 1.9 ma i dd2 halt mode f x = 2.0 mhz v dd = 3 v 10 % 0.3 1.0 ma f x = 400 khz v dd = 5 v 10 % 0.7 1.5 ma v dd = 3 v 10 % 0.3 0.9 ma v dd = 5 v 10 % 3.0 30 m a v dd = 3 v 10 % 2.0 30 m a notes 1. the pull-up resistors of p0f, reset, and int are mask options. 2. excluding the current of the a/d converter and poc circuit, and the current flowing into the internal pull-up resistor. r pull internal pull-up resistor note 1 i dd3 stop mode supply current note 2 v ol1 p0a, p0b, p0c, p0d, p0e 84 m pd17145(a1), 17147(a1), 17149(a1) cpu clock cycle time (instruction execution time) f int 0 400 khz reset low-level width t rsl rls low-level width t rlsl ac characteristics (v dd = 2.7 to 5.5 v, t a = e40 to +110 ?c) parameter symbol condition min. typ. max. unit v dd = 4.5 to 5.5 v 1.9 41 m s t cy v dd = 3.6 to 5.5 v 3.9 41 m s 7.9 41 m s int input frequency (tm0 count clock input) int high-, low-level width t inth, v dd = 4.5 to 5.5 v 10 m s (external interrupt input) t intl 50 m s v dd = 4.5 to 5.5 v 10 m s 50 m s v dd = 4.5 to 5.5 v 10 m s 50 m s remark t cy = 16/f x (f x : system clock oscillation frequency) interrupt input timing reset input timing rls input timing t intl t inth int reset t rsl rls t rlsl 85 m pd17145(a1), 17147(a1), 17149(a1) serial transfer operation (v dd = 2.7 to 5.5 v, t a = e40 to +110 c) parameter symbol condition min. typ. max. unit v dd = 4.5 to 5.5 v 2.0 m s 10 m s r l = 1 k w ,v dd = 4.5 to 5.5 v 2.0 m s c l = 100 pf 8 m s internal pull-up, v dd = 4.5 to 5.5 v 32 m s c l = 100 pf 64 m s v dd = 4.5 to 5.5 v 1.0 m s 5.0 m s sck high-, low-level t kh, r l = 1 k w ,v dd = 4.5 to 5.5 v t kcy /2 e 0.6 m s width t kl c l = 100 pf t kcy /2 e 1.2 m s internal pull-up, v dd = 4.5 to 5.5 v t kcy /2 e 12 m s c l = 100 pf t kcy /2 e 24 m s si setup time (to sck - )t sik 100 ns si hold time ( from sck - ) t ksi 100 ns r l = 1 k w , c l = 100 pf v dd = 4.5 to 5.5 v 0.8 m s so output delay time 1.4 m s from sck internal pull-up, v dd = 4.5 to 5.5 v 14 m s c l = 100 pf 26 m s remark r l : load resistance of output line c l : load capacitance of output line serial transfer timing input output sck cycle time t kcy input output t kso v dd r l c l output line sck si so t kcy t kl t kh t sik t ksi t kso output data input data 86 m pd17145(a1), 17147(a1), 17149(a1) a/d converter (v dd = 4.0 to 5.5 v, t a = e40 to +110 c) parameter symbol condition min. typ. max. unit resolution 888bit absolute accuracy note 1 2.5 v v ref v dd 1.5 lsb conversion time note 2 t conv 25 t cy m s analog input voltage v adin 0v ref v reference input voltage v ref 2.5 v dd v a/d converter circuit current i adc when a/d converter operates 1.0 2.0 ma v ref pin current i ref 0.1 0.3 ma notes 1. absolute accuracy excluding quantization error ( 0.5lsb) 2. time since a conversion start instruction has been executed until conversion ends (adcend = 1) (50 m s at 8 mhz). remark t cy = 16/f x (f x : system clock oscillation frequency) poc circuit (mask option note 1 ) (v dd = 2.7 to 5.5 v, t a = e40 to +110 c) parameter symbol condition min. typ. max. unit poc detection voltage note 2 v poc 3.6 4.0 4.45 v supply voltage fall speed t pocs 0.08 v/ms reset detection pulse width t samp 1ms poc circuit current i poc 3.0 10 m a notes 1. the poc circuit can be used in an application circuit that operates at v dd = 4.5 to 5.5 v, f x = 400 khz to 4 mhz. 2. this is the voltage at which the poc circuit clears its internal reset operation. the internal reset is cleared when v poc < v dd . 87 m pd17145(a1), 17147(a1), 17149(a1) oscillator characteristics (v dd = 2.7 to 5.5 v, t a = e40 to +110 c) resonator note symbol condition min. typ. max. unit 0.39 2.04 mhz ceramic resonator oscillation frequency v dd = 3.6 to 5.5 v 0.39 4.08 mhz v dd = 4.5 to 5.5 v 0.39 8.16 mhz note do not use a resonator whose oscillation growth time exceeds 2 ms. recommended ceramic resonator (t a = e40 to +110 c) recommended constants operating supply voltage [v] part number remark c1 [pf] c2 [pf] rd [k w ] min. max. csb400ja 220 220 5.6 2.7 5.5 csa2.00mga040 100 100 0 2.7 5.5 cst2.00mga040 unnecessary (c-contained type) 0 2.7 5.5 csa4.00mga 30 30 0 3.6 5.5 cst4.00mgwa unnecessary (c-contained type) 0 3.6 5.5 csa8.00mtza 30 30 0 4.5 5.5 cst8.00mtwa unnecessary (c-contained type) 0 4.5 5.5 external circuit example manufac- turer murata mfg. co. for automotive electronics x in x out rd c2 c1 88 m pd17145(a1), 17147(a1), 17149(a1) 23. characteristic curve (reference value) i ol vs. v ol characteristic example 1 (p0a, p0b, p0c) caution the absolute maximum rating is 15 ma (peak value) per pin. x in x out c2 operation mode (8 mhz) operation mode (4 mhz) operation mode (2 mhz) halt mode (8 mhz) halt mode (2 mhz) halt mode (4 mhz) 0 2.0 3.0 4.0 5.0 2.7 3.6 5.5 suppl y volta g e v dd [ v ] supply current i dd [ma] 1.0 2.0 3.0 4.0 (t a = 25 ?c) c1 csa 8.00mtza (c1 = c2 = 30 pf) csa 4.00mga (c1 = c2 = 30 pf) csa 2.00mga040 (c1 = c2 = 100 pf) (t a = 25 ?c) 20 15 10 5 0 123 low-level output voltage v ol [v] low-level output current i ol [ma] v dd = 5.0 v v dd = 4.5 v v dd = 3.5 v 89 m pd17145(a1), 17147(a1), 17149(a1) i ol vs. v ol characteristics example 2 (p0d, p0e) caution the absolute maximum rating is 30 ma (peak value) per pin. i oh vs. (v dd - v oh ) characteristic example caution the absolute maximum rating is e15 ma (peak value) per pin. (t a = 25 ?c) 30 20 10 0 12 low-level output volta g e v ol [v] low-level output current i ol [ma] v dd = 5.0 v v dd = 4.5 v v dd = 3.5 v e 5 0 high-level output current i oh [ma] e 10 e 15 e 20 12 v dd e v oh [v] 3 v dd = 5.0 v v dd = 4.5 v v dd = 3.5 v (t a = 25 ?c) 90 m pd17145(a1), 17147(a1), 17149(a1) 24. package drawings caution the es model differs from the mass-produced model in terms of outline dimensions and materials. refer to the drawing of the es model. 28 pin plastic shrink dip (400 mil) item millimeters inches a b c f g h i j k 28.46 max. 1.778 (t.p.) 3.2 0.3 0.51 min. 4.31 max. 2.67 max. l 0.17 10.16 (t.p.) 5.08 max. 8.6 n 0.85 min. 1.121 max. 0.106 max. 0.033 min. 0.126 0.012 0.020 min. 0.170 max. 0.200 max. 0.400 (t.p.) 0.339 0.007 0.070 (t.p.) s28c-70-400b-1 a b i j g d 0.50 0.10 0.020 m 0.25 0.010 +0.10 e0.05 r 0~15 0~15 +0.004 e0.005 +0.004 e0.003 notes each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. item "k" to center of leads when formed parallel. 1) 2) 28 15 114 m h c n f d m r k l 91 m pd17145(a1), 17147(a1), 17149(a1) p28gt-50-375b-1 item millimeters inches note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 18.2 max. 0.845 max. 1.27 (t.p.) 0.40 0.125 0.075 2.9 max. 2.50 0.2 10.3 0.3 7.2 0.2 1.6 0.2 0.15 0.8 0.2 0.12 0.10 0.717 max. 0.034 max. 0.050 (t.p.) 0.016 0.005 0.003 0.115 max. 0.098 0.406 0.283 0.063 0.008 0.006 0.031 0.005 0.004 +0.009 ?.008 a b c d e f g h i j k l m n +0.10 ?.05 +0.10 ?.05 +0.004 ?.002 +0.009 ?.008 +0.012 ?.013 +0.009 ?.008 +0.004 ?.003 28 pin plastic sop (375 mil) 28 15 a i m m d c n k detail of lead end e f g b h l j 114 3 +7 ? caution the es model differs from the mass-produced model in terms of outline dimension and materials. refer to the drawing of the es model. 92 m pd17145(a1), 17147(a1), 17149(a1) 28 pin ceramic shrink dip (400 mil) (for es) item millimeters inches a b c d f g h i j 28.0 max. 1.778 (t.p.) 0.8 min. 3.01.0 1.0 min. 5.1 max. 4.3 max. 2.7 0.460.05 1.103 max. 0.201 max. 0.0180.002 0.031 min. 0.1180.04 0.039 min. 0.106 0.170 max. 0.070 (t.p.) p28d-70-400b-1 a j notes 1) each lead centerline is located within 0.25 mm (0.01 inch) of its true position (t.p.) at maximum material condition. k l m 10.16 (t.p.) 9.84 0.250.05 0.400 (t.p.) 0.387 0.010 n 0.25 0.010 r 0~15? 0~15? +0.002 e0.003 2) ltem "k" to center of leads when formed parallel. m i g h f d n c b m r k l 28 15 114 93 m pd17145(a1), 17147(a1), 17149(a1) x28b-50b1 item millimeters inches a c d g i j k t 18.00.2 0.40.05 16.4 0.150.025 1.0 1.27 (t.p.) 1.520.15 8.40.15 0.709 0.05 (t.p.) 0.060.006 0.331 0.646 0.0060.001 0.039 the lengths of leads ( 1 ) and the height of potting ( 2 ) are not to be specified because the lead cutting process and the potting process are not controlled. +0.008 e0.009 0.016 +0.002 e0.003 +0.006 e0.007 28 pin ceramic sop (for es) note a i j 1 d c t 2 g k 94 m pd17145(a1), 17147(a1), 17149(a1) 25. recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for the other soldering conditions and methods, consult nec. table 25-1. soldering conditions of surface mount type m pd17145gt(a1)- : 28-pin plastic sop (375 mil) m pd17147gt(a1)- : 28-pin plastic sop (375 mil) m pd17149gt(a1)- : 28-pin plastic sop (375 mil) symbol of recommended soldering method soldering condition condition package peak temperature: 235 c, time: 30 seconds max. (210 c min.), number of times: 2 max., duration note : 7 (after that, prebaking is necessary for 20 hours at 125 c.) 95 m pd17145(a1), 17147(a1), 17149(a1) table 25-2. soldering conditions of insertion type m pd17145ct(a1)- : 28-pin plastic shrink dip (400 mil) m pd17147ct(a1)- : 28-pin plastic shrink dip (400 mil) m pd17149ct(a1)- : 28-pin plastic shrink dip (400 mil) soldering method soldering condition wave soldering (pin only) solder bath temperature: 260 ?c max., time: 10 seconds max. pin partial heating pin temperature: 300 ?c max., time: 3 seconds max. (per side of pin) caution when performing wave soldering, exercise care that only the pins are wetted with solder and that no part of the package must be wetted. 96 m pd17145(a1), 17147(a1), 17149(a1) appendix a. function comparison between m pd17145 subseries and the m pd17135a and 17137a m pd17145 m pd17147 m pd17149 m pd17135a m pd17137a rom 2 kb 4 kb 8 kb 2 kb 4 kb ram 110 4 bits 112 4 bits stack address stack 5 levels interrupt stack 3 levels instruction execution time 2 m s (8 mhz, 4.5 to 5.5 v) 2 m s (8 mhz, 4.5 to 5.5 v) (clock, operating voltage) 4 m s (4 mhz, 3.6 to 5.5 v) 4 m s (4 mhz, 2.7 to 5.5 v) 8 m s (2 mhz, 2.7 to 5.5 v) cmos i/o 12 (p0a, p0b, p0c) input 2 (p0f 0 , p0f 1 ) 1 (p1b 0 ) sense input 1 (int) 1 (int) i/o can be pulled up by mask option n-ch open-drain i/o 8 (p0d, p0e voltage: v dd ) 8 (p0d, p1a voltage: 9 v) p0d pull-up: software p0d pull-up: mask option p0e pull-up: software p1a pull-up: mask option internal pull-up resistor 100 k w typ. (except p0d) 100 k w typ. 10 k w typ. (p0d) a/d converter 8 bits 4 channels 8 bits 4 channels (operating voltage) (v dd = 4.0 to 5.5 v) (v dd = 4.5 to 5.5 v) reference voltage pin v ref (v ref = 2.5 v to v dd ) none (v ref = v adc = v dd ) 8-bit (tm0, tm1) 2 (timer output: tm1out) 2 (timer output: tm0out) tm0 clock: system clock/512 tm0 clock: system clock/256 system clock/64 system clock/64 system clock/16 system clock/16 int int tm1 clock: system clock/8192 tm1 clock: system clock/1024 system clock/128 system clock/512 system clock/16 system clock/256 tm0 count up tm0 count up basic interval (btm) 1 (also used as watchdog timer) 1 (also used as watchdog timer) count clock: system clock/16384 count clock: system clock/8192 system clock/4096 system clock/4096 system clock/512 tm0 count up system clock/16 int interrupt external 1 1 (with ac zero cross detection) internal 4 (tm0, tm1, btm, sio) sio 1 (clocked 3-wire) output latch independent of p0d 1 latch shared with p0d 1 latch standby function halt, stop halt, stop (can be released by rls input pin) timer 97 m pd17145(a1), 17147(a1), 17149(a1) m pd17145 m pd17147 m pd17149 m pd17135a m pd17137a oscillation stabilization 128 256 counts 512 256 counts wait time poc function mask option internal package 28-pin plastic sdip (400 mil) 28-pin plastic sop (375 mil) one-time prom m pd17p149 m pd17p137a caution the m pd17145 subseries is not pin-compatible with the m pd17135a and 17137a. the m pd17145 subseries does not include a product equivalent to the m pd17134a and 17136a (rc oscillation type). for the electrical specifications of each product, refer to the data sheet of the product. 98 m pd17145(a1), 17147(a1), 17149(a1) appendix b. development tools the following development tools are available for developing programs for the m pd17145(a1), 17147(a1), and 17149(a1): hardware notes 1. low-cost model: external power supply type 2. this is a product of ic corporation. for details, consult ic corporation (tokyo (03) 3447-3793). 3. two ev-97500gt-28s are supplied with the ep-17k28gt. five ev-9500gt-28s are separately available as a set. 4. these are products of ando electric corporation. for details, consult ando electric corporation (tokyo (03) 3733-1151). outline ie-17k, ie-17k-et, and emu-17k are in-circuit emulators that can be used with any products in the 17k series. ie-17k and ie-17k-et are connected to pc-9800 series or ibm pc/at ? as the host machine with rs-232-c. emu-17k is inserted into an expansion slot of the pc-9800 series. these in-circuit emulators operate as the emulator for a device when used in combination with the dedicated system evaluation board (se board) of the device. when man-machine interface, simplehost ? , is used a sophisticated debugging environment can be realized. emu-17k also has a function that allows real-time monitoring of the contents of the data memory. se-17145 is an se board for the m pd17145 subseries. it can be used alone to evaluate the system, or in combination with an in-circuit emulator for debugging. ep-17k28ct is an emulation probe for the 17k series 28-pin shrink dip (400 mil). ep-17k28gt is an emulation probe for the 17k series 28-pin sop (375 mil). it connects the se board and target system when used with ev-9500gt-28 note 3 . ev-9500gt-28 is an adapter for the 28-pin sop (375 mil). it is used to connect ep- 17k28gt and target system. af-9703, af-9704, af-9705, and af-9706 are prom programmers supporting the m pd17p149. by connecting programmer adapter af-9808m to these programmers, the m pd17p149 can be programmed. af-9808m is an adapter used to program the m pd17p149, in combination with af- 9703, af-9704, af-9705, or af-9706. name in-circuit emulator ie-17k, ie-17k-et note 1 , emu-17k note 2 se board (se-17145) emulation probe (ep-17k28ct) emulation probe (ep-17k28gt) conversion adapter (ev-9500gt-28 note 3 ) prom programmer note 4 (af-9703, af-9704, af-9705 or af-9706) programmer adapter note 4 (af-9808m) 99 m pd17145(a1), 17147(a1), 17149(a1) supply media 5"2hd 3.5"2hd 5"2hc 3.5"2hc 5"2hd 3.5"2hd 5"2hc 3.5"2hc 5"2hd 3.5"2hd 5"2hc 3.5"2hc order code m s5a10as17k m s5a13as17k m s7b10as17k m s7b13as17k m s5a10as17145 note m s5a13as17145 note m s7b10as17145 note m s7b13as17145 note m s5a10ie17k m s5a13ie17k m s7b10ie17k m s7b13ie17k os ms-dos ? pc dos ? ms-dos pc dos host machine pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at outline as17k is an assembler that can be used with any prod- ucts in the 17k series. to develop the program of the m pd17145(a1), 17147(a1), and 17149(a1), the as17k and a device file (as17145, as17147, or as17149) are used in combination. as17145, as17147, and as17149 are device files for the m pd17145(a1), 17147(a1), 17149(a1), and m pd17p149. they can be used in combination with the assembler for the 17k series (as17k). simplehost is software that serves as man-machine interface on windows ? when a program is developed by using an in-circuit emulator and a personal computer. ms-dos pc dos windows name 17k series assembler (as17k) device file as17145, as17147, as17149 support software (simplehost) software note m s as17145 includes as17145, as17147, and as17149. remark the version of the os supported is as follows: os version ms-dos ver. 3.30 to ver. 5.00a note pc dos ver. 3.1 to ver. 5.0 note windows ver. 3.0 to ver. 3.1 note although ms-dos ver.5.00/5.00a and pc dos ver. 5.0 have a task swap function, this function cannot be used with this software. 100 m pd17145(a1), 17147(a1), 17149(a1) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function. 101 m pd17145(a1), 17147(a1), 17149(a1) nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j97. 8 m pd17145(a1), 17147(a1), 17149(a1) simplehost is a trademark of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corpora- tion in the united states and/or other countries. pc/at and pc dos are trademarks of ibm corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 |
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